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Tue, 27 Oct 2020 02:31:19 +0000 (GMT) Received: from Madhavan.PrimaryTP (unknown [9.199.32.222]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 27 Oct 2020 02:31:19 +0000 (GMT) Subject: Re: [PATCH 5/5] powerpc/perf: use regs->nip when siar is zero To: Michael Ellerman , Christophe Leroy References: <20201021085329.384535-1-maddy@linux.ibm.com> <20201021085329.384535-5-maddy@linux.ibm.com> <6ad49bc4-6fc8-0cb9-2228-3da9fea3f0dc@csgroup.eu> <87r1prxd9e.fsf@mpe.ellerman.id.au> From: Madhavan Srinivasan Message-ID: <37d7fe94-696f-fc59-2756-7ea89525d4ae@linux.ibm.com> Date: Tue, 27 Oct 2020 08:01:18 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.11.0 MIME-Version: 1.0 In-Reply-To: <87r1prxd9e.fsf@mpe.ellerman.id.au> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.737 definitions=2020-10-26_20:2020-10-26, 2020-10-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 mlxlogscore=711 bulkscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 phishscore=0 adultscore=0 suspectscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2010270010 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: atrajeev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 10/22/20 6:55 AM, Michael Ellerman wrote: > Christophe Leroy writes: >> Le 21/10/2020 à 10:53, Madhavan Srinivasan a écrit : >>> In power10 DD1, there is an issue where the >>> Sampled Instruction Address Register (SIAR) >>> not latching to the sampled address during >>> random sampling. This results in value of 0s >>> in the SIAR. Patch adds a check to use regs->nip >>> when SIAR is zero. >> Why not use regs->nip at all time in that case, and not read SPRN_SIAR at all ? > Yeah that's a reasonable question. > > I can't really find anywhere in the ISA that explains it. > > I believe the main (or only?) reason is that interrupts might be > disabled when the PMU samples the instruction. So in that case the SIAR > will point at an instruction somewhere in interrupts-off code, whereas > the NIP will point to the location where we re-enabled interrupts and > took the PMU interrupt. sorry for the delayed response, was out. thats correct and also we see SIAR zeroing only for some of the events. We still want to use the SIAR address for the sample creation and use nip only if it  zero. Maddy > > cheers