4xx tlb questions

4xx tlb questions

[Mike Wolf]

Hi,
  I'm new to kernel development and have a question
on the 4xx.  Part of the tlb address is 8 bits from the
PID register.  I cannot find the code that sets the PID
register for user code.  I find code that sets the PID reg
to 0, and I find code that saves the current value of PID reg
and then setting it to 0 to do some work and then sets
it back.  I was expecting to see something in sched.c that
set the PID to some value from the task_struct on a context
switch.

Its not at all obvious to me how the PID is getting set.  The
only other option I'm aware of is to invalidate the TLB on
a context change, but I didnt see that either and the tlb
handlers imply something else because they save the current
value of the PID register.  If it was always 0 it wouldnt
need that
--
Mike Wolf
Cray Research
655-F Lone Oak Drive, Eagan, MN 55121
mwolf@cray.com          (651)683-5313

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Re: 4xx tlb questions

[ben bodley]

Mike Wolf wrote:

> Hi,
>   I'm new to kernel development and have a question
> on the 4xx.  Part of the tlb address is 8 bits from the
> PID register.  I cannot find the code that sets the PID
> register for user code.  I find code that sets the PID reg
> to 0, and I find code that saves the current value of PID reg
> and then setting it to 0 to do some work and then sets
> it back.  I was expecting to see something in sched.c that
> set the PID to some value from the task_struct on a context
> switch.
>
> Its not at all obvious to me how the PID is getting set.  The
> only other option I'm aware of is to invalidate the TLB on
> a context change, but I didnt see that either and the tlb
> handlers imply something else because they save the current
> value of the PID register.  If it was always 0 it wouldnt
> need that
>

mike,

the pid is set with the 'set_context()' function inside arch/ppc/head_4xx.S,
(see also include/asm/mmu_context.h) and some adjustments are needed for 4xx
core (see montavista's latest patch)..

the context (as far as i see it) seems to be based on the running vma's in the
system.. (allocated for process memory req's), when a new process is spawned a
new context is created for memory accessed by that process..

cheers,

ben


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Re: 4xx tlb questions

[Wang Yong]

the PID reg corresponds to TID field of TLB Entry when
new entry is inserted and va is translated. if the TID of
some entry is set to 0, then this entry can be used for
translation by every process. in scenario of creating
new TLB entry and process switching, you should set PID
reg. and the TLBs used by virtual space of kernel is inserted
into TLB with the TID set as 0 so that PID need not to be
changed when enter kernel(system call or interrupt and so on).

w.y.
--
Wang Yong - DCS at Tsinghua Univ.

EMAIL: wyong@acm.org (CC to wung_y@yahoo.com pls :-)
PHONE: 010-62788076(Lab)
       010-62775899(Dorm)
Dorm : 22#606, Tsinghua Univ.


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