From: Alistair Popple <alistair@popple.id.au>
To: Michael Ellerman <mpe@ellerman.id.au>
Cc: aneesh.kumar@linux.ibm.com, mikey@neuling.org,
linuxppc-dev@lists.ozlabs.org, npiggin@gmail.com
Subject: Re: [PATCH v2 1/7] powerpc: Add new HWCAP bits
Date: Wed, 20 May 2020 13:29:10 +1000 [thread overview]
Message-ID: <3938008.enqZtH4Sbd@townsend> (raw)
In-Reply-To: <871rnf49a6.fsf@mpe.ellerman.id.au>
On Wednesday, 20 May 2020 12:42:09 PM AEST Michael Ellerman wrote:
> Alistair Popple <alistair@popple.id.au> writes:
> > POWER10 introduces two new architectural features - ISAv3.1 and matrix
> > multiply accumulate (MMA) instructions. Userspace detects the presence
> > of these features via two HWCAP bits introduced in this patch. These
> > bits have been agreed to by the compiler and binutils team.
>
> Do we have an explanation of why we're exposing MMA separately.
>
> I believe it's because ISA v3.1 says that MMA is optional, in the table
> on page ix?
Right, MMA is an optional feature and software should check for its presence
prior to use. This is explicitly stated in the ISA on pg. 574:
7.6.1.12 VSX Matrix-Multiply Assist (MMA) Instructions
The MMA facility is optional. Software that uses this facility should test for
its availability and provide an alternate
execution path.
The HWCAP bit is the mechanism for that. I can add the description to the
commit message.
- Alistair
> cheers
>
> > diff --git a/arch/powerpc/include/uapi/asm/cputable.h
> > b/arch/powerpc/include/uapi/asm/cputable.h index
> > 540592034740..2692a56bf20b 100644
> > --- a/arch/powerpc/include/uapi/asm/cputable.h
> > +++ b/arch/powerpc/include/uapi/asm/cputable.h
> > @@ -50,6 +50,8 @@
> >
> > #define PPC_FEATURE2_DARN 0x00200000 /* darn random number insn */
> > #define PPC_FEATURE2_SCV 0x00100000 /* scv syscall */
> > #define PPC_FEATURE2_HTM_NO_SUSPEND 0x00080000 /* TM w/out suspended
> > state */>
> > +#define PPC_FEATURE2_ARCH_3_1 0x00040000 /* ISA 3.1 */
> > +#define PPC_FEATURE2_MMA 0x00020000 /* Matrix Multiply Accumulate */
> >
> > /*
> >
> > * IMPORTANT!
next prev parent reply other threads:[~2020-05-20 3:31 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 0:31 [PATCH v2 0/7] Base support for POWER10 Alistair Popple
2020-05-19 0:31 ` [PATCH v2 1/7] powerpc: Add new HWCAP bits Alistair Popple
2020-05-19 3:20 ` Michael Neuling
2020-05-19 17:48 ` Paul A. Clarke
2020-05-20 2:42 ` Michael Ellerman
2020-05-20 3:29 ` Alistair Popple [this message]
2020-05-19 0:31 ` [PATCH v2 2/7] powerpc: Add support for ISA v3.1 Alistair Popple
2020-05-19 4:04 ` Jordan Niethe
2020-05-19 5:45 ` Alistair Popple
2020-05-19 0:31 ` [PATCH v2 3/7] powerpc/dt_cpu_ftrs: Advertise support for ISA v3.1 if selected Alistair Popple
2020-05-19 0:31 ` [PATCH v2 4/7] powerpc/dt_cpu_ftrs: Set current thread fscr bits Alistair Popple
2020-05-19 0:31 ` [PATCH v2 5/7] powerpc/dt_cpu_ftrs: Enable Prefixed Instructions Alistair Popple
2020-05-19 0:31 ` [PATCH v2 6/7] powerpc/dt_cpu_ftrs: Add MMA feature Alistair Popple
2020-05-19 14:49 ` Paul A. Clarke
2020-05-19 15:05 ` Segher Boessenkool
2020-05-19 15:22 ` Paul A. Clarke
2020-05-19 15:28 ` Segher Boessenkool
2020-05-19 15:49 ` Paul A. Clarke
2020-05-19 17:51 ` Paul A. Clarke
2020-05-19 23:56 ` Alistair Popple
2020-05-19 0:31 ` [PATCH v2 7/7] powerpc: Add POWER10 architected mode Alistair Popple
2020-05-19 3:58 ` Jordan Niethe
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