Trying to enable backside on a G4

Trying to enable backside on a G4

[Guillaume Laurès]

Hi,

I'm just starting writing kernel-level code :-), and I was trying to set
the L2CR register on a G4 upgrade for a PCI PowerMac (actually a
8600/250 upgraded with a XLR8 MACh Carrier G4 350/233)

So this is my code, extracted from arch/ppc/kernel/setup.c :

/* Programme réalisant l'initialisation du registre l2cr sur G3 ou G4
   08/07/00 Guillaume Laures
*/

#include <linux/config.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/reboot.h>
#include <linux/delay.h>
#include <linux/blk.h>


int main()
{
  unsigned long val = 0xb5100000;       // XLR8 MACh Carrier G4 350/233
//  unsigned long val = 0xb9100000;       // XLR8 MACh Carrier G4
350/175
//  unsigned long val = 0xb9000000;       // Apple G4 450/225 SawTooth
cpu module
//  unsigned long val = 0xb5000000;       // Apple G4 450/300 ?

  if ( ((_get_PVR() >> 16) == 8) || ((_get_PVR() >> 16) == 12) )
    {
      printk(KERN_INFO "l2cr set to %lx\n", val);
      _set_L2CR(0);
//      _set_L2CR(val);
      return 0;
    }
  else
    return 1;
}

And here is my makefile :

all:            l2cr_ini

clean:
                rm -f l2cr_ini l2cr_ini.o

l2cr_ini.o:     l2cr_ini.c
                gcc -D__KERNEL__ -I/usr/src/linux/include -Wall
-Wstrict-prototypes -O2 -fomit-frame-pointer -fno-strict-aliasing
-D__powerpc__ -fsigned-char -msoft-float -pipe -fno-builtin -ffixed-r2
-Wno-uninitialized -mmultiple -mstring -c l2cr_ini.c

l2cr_ini:       l2cr_ini.o
                gcc -o l2cr_ini l2cr_ini.o

I can get the .o, but obviously not the executable, does anyone could
help me get it please ?

--
Guillaume


** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/

Re: Trying to enable backside on a G4

[Michel Lanners]

Hi Guillaume,

On   8 Jul, this message from Guillaume Laurès echoed through cyberspace:
> I'm just starting writing kernel-level code :-), and I was trying to set
> the L2CR register on a G4 upgrade for a PCI PowerMac (actually a
> 8600/250 upgraded with a XLR8 MACh Carrier G4 350/233)

If you're working on 2.4.0-style kernels, here is a patch that
implements this functionality as a kernel command line option.

If you are trying to produce a standalone program, your example code
will not work. It will only work inside the kernel, not from userspace.
You could try to build it as a module....

But then again, you can easily set the l2cr from userspace. I have this
in my /etc/rc.d/rc.sysinit:

action "Mounting proc filesystem" mount -n -t proc /proc /proc

# Now that /proc is available, set up level2 cache:
echo 0 > /proc/sys/kernel/l2cr
echo '0x29200000' > /proc/sys/kernel/l2cr
echo '0xa9200000' > /proc/sys/kernel/l2cr
action "Enabling level2 cache" echo -n

doing a 'cat /proc/sys/kernel/l2cr' will show you the current setting of
l2cr.

Be aware that there might be problems with just using the echo>
technique, as the cache needs to be invalidated before enabling it.
Normally that should happen automagically; however it didn't work for
me. That's why there are two 'echo's above.

My final l2cr value is:

[mlan@piglet ~]$ cat /proc/sys/kernel/l2cr
0xa9000000:  enabled, no parity, 512KB, +2 clock, pipelined burst SRAM, copy-back, 0.5ns hold

Have fun

Michel

-------------------------------------------------------------------------
Michel Lanners                 |  " Read Philosophy.  Study Art.
23, Rue Paul Henkes            |    Ask Questions.  Make Mistakes.
L-1710 Luxembourg              |
email   mlan@cpu.lu            |
http://www.cpu.lu/~mlan        |                     Learn Always. "


** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/

Re: Trying to enable backside on a G4

[Guillaume Laurès]

Michel Lanners a écrit :

>
> If you're working on 2.4.0-style kernels, here is a patch that
> implements this functionality as a kernel command line option.

Hum, did you forget to join the patch ???

And what about the l2cr=xxxxxxxx option in the next kernels, will it be re-enabled or should we
keep on user-space ?

>
>
> If you are trying to produce a standalone program, your example code
> will not work. It will only work inside the kernel, not from userspace.
> You could try to build it as a module....

OK, let's schedule this for later...

>
>
> But then again, you can easily set the l2cr from userspace. I have this
> in my /etc/rc.d/rc.sysinit:

I followed your setup and put :

        echo -n "Enabling level2 cache..."
        echo 0 > /proc/sys/kernel/l2cr
        echo '0x35300000' > /proc/sys/kernel/l2cr
#disabled,no parity,1MB,+1.5 clock,pipelined burst SRAM,data only,global invalidate,ZZ
enabled,copy-back,0.5ns hold
        echo '0xb5100000' > /proc/sys/kernel/l2cr
#enabled,no parity,1MB,+1.5 clock,pipelined burst SRAM,data only,ZZ enabled,copy-back,0.5ns hold

        echo

Since :
 - GrabG3CacheSetting (slightly modified to accept any processor or it would complain that I
don't have a G3...) from BenH told me that XLR8's extension sets my G4's L2CR to 0xb5100000
 - I don't really understand what the the L2I bit stands for, is it necessary to set it on the
second echo too as you do ?

>
> Be aware that there might be problems with just using the echo>
> technique, as the cache needs to be invalidated before enabling it.
> Normally that should happen automagically; however it didn't work for
> me. That's why there are two 'echo's above.

So may be it's viser to do as a general rule :

echo 0 > /proc/sys/kernel/l2cr # (disable)
echo '0x00200000' > /proc/sys/kernel/l2cr # (invalidate)
echo '0x_what_your_card_supports' /proc/sys/kernel/l2cr # (set up and enable)

>
>
> My final l2cr value is:
>
> [mlan@piglet ~]$ cat /proc/sys/kernel/l2cr
> 0xa9000000:  enabled, no parity, 512KB, +2 clock, pipelined burst SRAM, copy-back, 0.5ns hold

gom@pm8600:~$ cat /proc/sys/kernel/l2cr
b5100000:  enabled,no parity,1MB,+1.5 clock,pipelined burst SRAM,data only,ZZ
enabled,copy-back,0.5ns hold
And kernel compilation is now at least twice as fast...

>
>
> Have fun

Oh, I did ;-)

--
Guillaume


** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/

Re: Trying to enable backside on a G4

[Michel Lanners]

[-- Attachment #1: Type: TEXT/plain, Size: 3409 bytes --]

Hi all,

On   8 Jul, this message from Guillaume Laurès echoed through cyberspace:
> Michel Lanners a écrit :
>>
>> If you're working on 2.4.0-style kernels, here is a patch that
>> implements this functionality as a kernel command line option.
>
> Hum, did you forget to join the patch ???

Ooopss.. sorry about that. Wrote the mail this morning in a hurry ;-)

Attached are actually two patches: the first one fixes the output of
'cat /proc/sys/kernel/l2cr', as it contains some errors and omissions.
This part is only needed on 2.2.x and old 2.3.x kernels; it's integrated
in 2.4.0-something.

The second patch adds command line functionality for 2.3/2.4 kernels.

> And what about the l2cr=xxxxxxxx option in the next kernels, will it be re-enabled or should we
> keep on user-space ?

Keep it in userspace for now. It's better to have it in the kernel, as
the l2 cache has an influence on the bogomips calculation (at least in
2.2 kernels), hence affects the accuracy of kernel timing loops. I
haven't noticed any adverse effects, however.

I'll have to check whether all the steps I've taken to enable the cache
are actually needed, since all the invalidate stuff should be handled by
the function I'm calling. But it didn't work last I tried.... Once
that's decided, I will resubmit the command line patch.

> I followed your setup and put :
>
>         echo -n "Enabling level2 cache..."
>         echo 0 > /proc/sys/kernel/l2cr
>         echo '0x35300000' > /proc/sys/kernel/l2cr
> #disabled,no parity,1MB,+1.5 clock,pipelined burst SRAM,data only,global invalidate,ZZ
> enabled,copy-back,0.5ns hold
>         echo '0xb5100000' > /proc/sys/kernel/l2cr
> #enabled,no parity,1MB,+1.5 clock,pipelined burst SRAM,data only,ZZ enabled,copy-back,0.5ns hold

Don't take the text translation above too serious; it comes from the
partly bogus 2.2 kernel.... Other than that, as you have seen ;-), it
works.

> Since :
>  - GrabG3CacheSetting (slightly modified to accept any processor or it would complain that I
> don't have a G3...) from BenH told me that XLR8's extension sets my G4's L2CR to 0xb5100000

Yeah, could you submit that back to Ben? I've noticed that as well when
I started to play l2cr...

>  - I don't really understand what the the L2I bit stands for, is it necessary to set it on the
> second echo too as you do ?

Since you don't know what's leftover in the cache when you enable it,
you need to invalidate it first. And you need to make sure invalidation
has completed before actually turning the cache on. There's also a PLL
loop stabilizing issue, since you are setting a new value to the cache's
clocking. The steps taken are documented somehwere, I think in the
PowerPC manuals.

> So may be it's viser to do as a general rule :
>
> echo 0 > /proc/sys/kernel/l2cr # (disable)
> echo '0x00200000' > /proc/sys/kernel/l2cr # (invalidate)
        ^^^^^^^^^^
'Or' that with your requested setting, minus the enable bit, so that the
PLL for the cache's clock can stabilize.

> And kernel compilation is now at least twice as fast...

:-))

Michel

-------------------------------------------------------------------------
Michel Lanners                 |  " Read Philosophy.  Study Art.
23, Rue Paul Henkes            |    Ask Questions.  Make Mistakes.
L-1710 Luxembourg              |
email   mlan@cpu.lu            |
http://www.cpu.lu/~mlan        |                     Learn Always. "

[-- Attachment #2: l2cr-display.diff --]
[-- Type: TEXT/plain, Size: 1760 bytes --]

--- linux-2.2.15/arch/ppc/kernel/ppc_htab.c	Thu Aug 26 21:51:03 1999
+++ linux-work/arch/ppc/kernel/ppc_htab.c	Fri Aug 27 19:44:57 1999
@@ -595,19 +595,24 @@
 			if (!first)
 				*p++ = '\t';
 			val = _get_L2CR();
-			p += sprintf(p, "%08x: ", val);
-			p += sprintf(p, " %s",
-				     (val&0x80000000)?"enabled":"disabled");
-			p += sprintf(p,",%sparity",(val&0x40000000)?"":"no ");
-			p += sprintf(p, ",%s", sizestrings[(val >> 28) & 3]);
-			p += sprintf(p, ",%s", clockstrings[(val >> 25) & 7]);
-			p += sprintf(p, ",%s", typestrings[(val >> 23) & 0x2]);
-			p += sprintf(p,"%s",(val>>22)&1?"":",data only");
-			p += sprintf(p,"%s",(val>>20)&1?",ZZ enabled":"");
-			p += sprintf(p,",%s",(val>>19)&1?"write-through":"copy-back");
-			p += sprintf(p,",%sns hold", holdstrings[(val>>16)&3]);
+			p += sprintf(p, "0x%08x: ", val);
+			p += sprintf(p, " %s", (val >> 31) & 1 ? "enabled" :
+				     	"disabled");
+			p += sprintf(p, ", %sparity", (val>>30)&1 ? "" : "no ");
+			p += sprintf(p, ", %s", sizestrings[(val >> 28) & 3]);
+			p += sprintf(p, ", %s", clockstrings[(val >> 25) & 7]);
+			p += sprintf(p, ", %s", typestrings[(val >> 23) & 2]);
+			p += sprintf(p, "%s", (val>>22)&1 ? ", data only" : "");
+			p += sprintf(p, "%s", (val>>20)&1 ? ", ZZ enabled": "");
+			p += sprintf(p, ", %s", (val>>19)&1 ? "write-through" :
+					"copy-back");
+			p += sprintf(p, "%s", (val>>18)&1 ? ", testing" : "");
+			p += sprintf(p, ", %sns hold",holdstrings[(val>>16)&3]);
+			p += sprintf(p, "%s", (val>>15)&1 ? ", DLL slow" : "");
+			p += sprintf(p, "%s", (val>>14)&1 ? ", diff clock" :"");
+			p += sprintf(p, "%s", (val>>13)&1 ? ", DLL bypass" :"");

-			p += sprintf(p,"\n");
+			p += sprintf(p, "\n");

 			len = strlen(buf);
 			if (len > left)

[-- Attachment #3: l2cr-cmdline.diff --]
[-- Type: TEXT/plain, Size: 688 bytes --]

diff -uNr /mnt/r4/usr/src/linux-2.3.paul/arch/ppc/kernel/setup.c /usr/src/linux/arch/ppc/kernel/setup.c
--- /mnt/r4/usr/src/linux-2.3.paul/arch/ppc/kernel/setup.c	Fri Jun 16 13:32:29 2000
+++ /usr/src/linux/arch/ppc/kernel/setup.c	Sun Jun 25 00:15:03 2000
@@ -664,10 +664,14 @@
 	{
 		unsigned long val = simple_strtoul(str, NULL, 0);
 		printk(KERN_INFO "l2cr set to %lx\n", val);
-		_set_L2CR(0);
-		_set_L2CR(val);
+		val |= 0x200000;		/* perform global invalidate */
+		_set_L2CR(0); 			/* disable cache */
+		_set_L2CR(val & ~0x80000000);	/* set cache parameters */
+		_set_L2CR(val);			/* and enable it */
 	}
 }
+
+__setup("l2cr=", ppc_setup_l2cr);

 void __init ppc_init(void)
 {

Re: Trying to enable backside on a G4

[Guillaume Laurès]

[-- Attachment #1: Type: text/plain, Size: 4347 bytes --]



Michel Lanners a écrit :

>
> Attached are actually two patches: the first one fixes the output of
> 'cat /proc/sys/kernel/l2cr', as it contains some errors and omissions.
> This part is only needed on 2.2.x and old 2.3.x kernels; it's integrated
> in 2.4.0-something.

Yes it is.

>
>
> The second patch adds command line functionality for 2.3/2.4 kernels.

Hum, it was included already in 2.4 from linuxcare.

I attached what gives a boot on my G4/8600 with "as it comes options in menuconfig" (exept for the
Adaptec stuff which I had to put in a module or I would still get forever
"SCSI host 2 channel 0 reset (pid 1942) timed out - trying harder
SCSI bus is being reset for host 2 channel 0."

What can I say :
l2cr seems not to be enabled, as confirms a cat /proc/... later
There is a conflict on the Adaptec 3940UW board which wasn't there on 2.2
There is still the "SCSI bus is being reset for host..." problem for the usable half of the card (may
be it's a firmware issue, I use the 4.1/AV firmaware)
eth0 and eth1 have been swapped, which is not cool since this box is may IP-Masqu box...

>
> I'll have to check whether all the steps I've taken to enable the cache
> are actually needed, since all the invalidate stuff should be handled by
> the function I'm calling. But it didn't work last I tried.... Once
> that's decided, I will resubmit the command line patch.

Taken from Motorola's G4 User's Manual is the following :

3.7.4 L2 Cache Initialization
Following a power-on or hard reset, the L2 cache and the L2 cache DLL are disabled
initially. Before enabling the L2 cache, the L2 cache DLL must first be configured through
the L2CR register, and the DLL must be allowed 640 L2 cache clock periods to achieve
phase lock. Before enabling the L2 cache, other configuration parameters must be set in the
L2CR, and the L2 cache tags must be globally invalidated. The L2 cache should be
initialized during system start-up.
The sequence for initializing the L2 cache is as follows:
1.  (automatically performed by the assertion of HRESET).
2. Disable L2 cache by clearing L2CR[L2E].
3. Set the L2CR[L2CLK] bits to the desired clock divider setting. Setting a nonzero
value automatically enables the DLL. All other L2 cache configuration bits should
be set to properly configure the L2 cache interface for the SRAM type, size, and
interface timing required.
4. Wait for the L2 cache DLL to achieve phase lock. This can be timed by setting the
decrementer for a time period equal to 640 L2 cache clocks, or by performing an L2
cache global invalidate.
5. Perform an L2 cache global invalidate. The global invalidate could be performed
before enabling the DLL, or in parallel with waiting for the DLL to stabilize. Refer
to Section 3.7.3.7, "L2 Cache Global Invalidation," for more information about L2
cache global invalidation. Note that a global invalidate always takes much longer
than it takes for the DLL to stabilize.
6. After the DLL stabilizes, an L2 cache global invalidate has been performed, and the
other L2 cache configuration bits have been set, enable the L2 cache for normal
operation by setting the L2CR[L2E] bit to 1.

So I attached a correct (I think) user-space script called L2BS_enable.sh which I'm going to
propagate on linuxppc-users, tell me what you think about. I will try to work on kernel space then.

I'm just unsure of the behaviour of :
while test 1 = $((`cat /proc/sys/kernel/l2cr | awk -F : '{print $1}'`&0x00000001)); do wait; done

I couldn't test this loop.

>
>
> > Since :
> >  - GrabG3CacheSetting (slightly modified to accept any processor or it would complain that I
> > don't have a G3...) from BenH told me that XLR8's extension sets my G4's L2CR to 0xb5100000
>
> Yeah, could you submit that back to Ben? I've noticed that as well when
> I started to play l2cr...

I did, but it's not good yet. Here is what I did :
Original code is :
[...]
if (cpuFamily != gestaltCPU750)
 {
  printf("Error, CPU is not a G3\n");
  exit(0);
 }
 printf ("Getting value of G3 L2CR register ...\n");
[...]

I put :
[...]
 if ((cpuFamily != gestaltCPU750) || (cpuFamily != gestaltCPU7400))
 {
  printf("Error, CPU is not a G3, nor a G4\n");
  exit(0);
 }
[...]
but it doesn't compile, so I had to comment out the whole test... Does anybody knows how to identify
a G4 under MacOS ?




Bye bye,


--
Guillaume


[-- Attachment #2: Document --]
[-- Type: application/octet-stream, Size: 5404 bytes --]

Total memory = 192MB; using 1024kB for hash table (at c0300000)
Linux version 2.4.0-test1-ac21 (root@pm8600) (gcc version 2.95.2 20000313 (Debian GNU/Linux)) #2 Sun Jul 9 13:16:00 CEST 2000
PCI buses 0..1 controlled by bandit at f2000000
Cache coherency enabled for bandit/PSX at f7fed000
PCI bus 2 controlled by chaos at f0000000
On node 0 totalpages: 49152
zone(0): 49152 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: root=/dev/sda5 video=controlfb:vmode:18,cmode:8 l2cr=b5100000 devfs=nomount 
l2cr set to 0
System has 32 possible interrupts
via_calibrate_decr: decrementer_count = 124991 (749950 ticks)
Console: colour dummy device 80x25
Calibrating delay loop... 699.60 BogoMIPS
Memory: 188892k available (1640k kernel code, 864k data, 300k init) [c0000000,cc000000]
Dentry-cache hash table entries: 32768 (order: 6, 262144 bytes)
Buffer-cache hash table entries: 16384 (order: 4, 65536 bytes)
Page-cache hash table entries: 65536 (order: 6, 262144 bytes)
kmem_create: Poisoning requested, but con given - bdev_cache
Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
kmem_create: Poisoning requested, but con given - inode_cache
kmem_create: Poisoning requested, but con given - file lock cache
POSIX conformance testing by UNIFIX
PCI: Probing PCI hardware
PCI: Address space collision on region 1 of device Adaptec AHA-3940U/UW / AIC-7882U
PCI: Address space collision on region 6 of device Adaptec AHA-3940U/UW / AIC-7882U
PCI: Address space collision on region 0 of device Adaptec AHA-3940U/UW / AIC-7882U (#2)
PCI: Address space collision on region 1 of device Adaptec AHA-3940U/UW / AIC-7882U (#2)
PCI: Address space collision on region 6 of device Adaptec AHA-3940U/UW / AIC-7882U (#2)
usb.c: registered new driver hub
Linux NET4.0 for Linux 2.3
Based upon Swansea University Computer Society NET3.039
kmem_create: Poisoning requested, but con given - skbuff_head_cache
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP, IGMP
IP: routing cache hash table of 2048 buckets, 16Kbytes
TCP: Hash tables configured (established 16384 bind 16384)
Starting kswapd v1.6
controlfb: Memory bank 1 present, bank 2 absent, total VRAM 2MB
Monitor sense value = 0x623, using video mode 18 and color mode 0.
Console: switching to colour frame buffer device 144x54
fb0: control display adapter
PowerMac Z8530 serial driver version 2.0
tty00 at 0xcd809020 (irq = 15) is a Z8530 ESCC, port = modem
tty01 at 0xcd810000 (irq = 16) is a Z8530 ESCC, port = printer
pty: 256 Unix98 ptys configured
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
loop: registered device at major 7
loop: enabling 8 loop devices
Uniform Multi-Platform E-IDE driver Revision: 6.31
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
fd0: SWIM3 floppy controller 
scsi0 : MESH
scsi1 : 53C94
scsi : 2 hosts.
mesh: target 0 synchronous at 5.0 MB/s
  Vendor: SEAGATE   Model: ST34520N          Rev: 1281
  Type:   Direct-Access                      ANSI SCSI revision: 02
Detected scsi disk sda at scsi0, channel 0, id 0, lun 0
mesh: target 3 synchronous at 5.0 MB/s
  Vendor: PIONEER   Model: DVD-ROM DVD-303   Rev: 1.10
  Type:   CD-ROM                             ANSI SCSI revision: 02
Detected scsi CD-ROM sr0 at scsi0, channel 0, id 3, lun 0
  Vendor: IOMEGA    Model: ZIP 100           Rev: E.08
  Type:   Direct-Access                      ANSI SCSI revision: 02
Detected scsi removable disk sdb at scsi0, channel 0, id 5, lun 0
scsi : detected 1 SCSI cdrom 2 SCSI disks total.
sr0: scsi3-mmc drive: 0x/0x cd/rw xa/form2 cdda tray
Uniform CD-ROM driver Revision: 3.11
SCSI device sda: hdwr sector= 512 bytes. Sectors= 8888924 [4340 MB] [4.3 GB]
Partition check:
 /dev/scsi/host0/bus0/target0/lun0: p1 p2 p3 p4 p5 p6 p7 p8
sdb : READ CAPACITY failed.
sdb : status = 0, message = 00, host = 0, driver = 08 
sdb : extended sense code = 2 
sdb : block size assumed to be 512 bytes, disk size 1GB.  
 /dev/scsi/host0/bus0/target5/lun0: I/O error: dev 08:10, sector 0
 unable to read partition table
eth0: DC21140 at 0x2000 (PCI bus 0, device 15), h/w address 00:00:94:a9:70:7c,
eth0: Using generic MII device control. If the board doesn't operate, 
please mail the following dump to the author:

MII device address: 1
MII CR:  3100
MII SR:  7809
MII ID0: 181
MII ID1: b802
MII ANA: 5e1
MII ANC: 0
MII 16:  640
MII 17:  f010
MII 18:  6800

      and requires IRQ25 (provided by PCI BIOS).
de4x5.c:V0.545 1999/11/28 davies@maniac.ultranet.com
Macintosh ADB mouse driver installed.
eth1: MACE at 00:05:02:ce:c6:1d, chip revision 25.64
DMA sound driver installed, using 4 buffers of 32k.
adb: CUDA driver v0.5 for Unified ADB.
adb devices: [2]: 2 5 [3]: 3 1
ADB keyboard at 2, handler set to 3
ADB mouse at 3, handler set to 2
Macintosh non-volatile memory driver v1.0
usb.c: registered new driver hid
mice: PS/2 mouse device common for all mice
devfs: v0.96 (20000430) Richard Gooch (rgooch@atnf.csiro.au)
devfs: boot_options: 0x2
kmem_create: Forcing size word alignment - nfs_fh
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 300k init 36k prep 8k chrp
Adding Swap: 196600k swap-space (priority -1)
eth0: media is 100Mb/s.
eth0: media is TP.
eth0: media is 100Mb/s.
arpwatch uses obsolete (PF_INET,SOCK_PACKET)
device eth1 entered promiscuous mode
eth0: media is TP.

[-- Attachment #3: Unknown Document --]
[-- Type: application/x-sh, Size: 1703 bytes --]

Re: Trying to enable backside on a G4

[Benjamin Herrenschmidt]

>
>So I attached a correct (I think) user-space script called L2BS_enable.sh
>which I'm going to
>propagate on linuxppc-users, tell me what you think about. I will try to
>work on kernel space then.
>
>I'm just unsure of the behaviour of :
>while test 1 = $((`cat /proc/sys/kernel/l2cr | awk -F : '{print
>$1}'`&0x00000001)); do wait; done

I'd rather fix the kernel code. The set_L2CR function in the kernel is
supposed to already handle all that work of waiting for the cache,
invalidating, etc...

Ben.

** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/

Re: Trying to enable backside on a G4

[Michel Lanners]

Hi all,

On   9 Jul, this message from Benjamin Herrenschmidt echoed through cyberspace:
>>I'm just unsure of the behaviour of :
>>while test 1 = $((`cat /proc/sys/kernel/l2cr | awk -F : '{print
>>$1}'`&0x00000001)); do wait; done
>
> I'd rather fix the kernel code. The set_L2CR function in the kernel is
> supposed to already handle all that work of waiting for the cache,
> invalidating, etc...

I fully agree. Just didn't have the time to do so.... there were always
more important bugs to chase ;-)

Michel

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