Re:Re: Local sdram in 8260 board

Re:Re: Local sdram in 8260 board

[zzh]

>This could be the setup of the SDRAM control word. When the cache is enabled it
>begins bursting data from the SDRAM. When the SDRAM control word is not set to
>burst 32 bytes it will cause the memory exception.
>
>Dan Malek wrote:
>
I guess it maybe error in local sdram memc init.I follow the code provided by motorola. After machine check,i check location in
IMM related to local sdram error reporting and cannot find some
hint.And SRR1 does not provide any hint too.Do you think the
init value i program the memc and register values in machine check
will help?
>> zzh wrote:
>>
>> > ...it will get machine check exception
>> > at address 0x1000004 which is in the local sdram.When i disable the
>> > cache ,it will work.
>>
>> It sounds like something is wrong with your memory controller
>> configuration.  The cache enable/disable also affect the type of
>> bus cycles that are used to access memory.
>>
>>         -- Dan
>>


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Re:Re: Local sdram in 8260 board

[zzh]

>zzh wrote:
>
>> ...it will get machine check exception
>> at address 0x1000004 which is in the local sdram.When i disable the
>> cache ,it will work.
>
>
>It sounds like something is wrong with your memory controller
>configuration.  The cache enable/disable also affect the type of
>bus cycles that are used to access memory.
Aha, I read the 8260 manual charpter 10 and find it will generate
TEA if core try to burst access local bus address space.Why this restriction?
Maybe this is the reason of Machine Check.
>
>

>	-- Dan


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