* error in assumptions in the handling of interrupts.
@ 2000-07-28 12:13 Ralph Blach
2000-07-28 15:13 ` Dan Malek
0 siblings, 1 reply; 3+ messages in thread
From: Ralph Blach @ 2000-07-28 12:13 UTC (permalink / raw)
To: linuxppc-embedded
I would like explain a bug which I found in the 4xx interrupt controller
code yesterday.
In the ppc4xx_pic.c code their is a routine called
ppcxxx_aic_disable_and_ack.
The purpose of this code is disable interrupts on the level and reset
the ISR.
This will NOT work because for Level interrupts, the ISR will cannot be
reset until
the interrupting source is cleared.
The ack to reset the ISR for interrupt must go in the
ppcxxx_aic_enable
routine which irq.c calls after the interrupt routine has been
cleared.
Chip Blach
IBM MicroElectronics
Raleigh, NC.
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: error in assumptions in the handling of interrupts.
2000-07-28 12:13 error in assumptions in the handling of interrupts Ralph Blach
@ 2000-07-28 15:13 ` Dan Malek
2000-07-28 17:30 ` Frank Rowand
0 siblings, 1 reply; 3+ messages in thread
From: Dan Malek @ 2000-07-28 15:13 UTC (permalink / raw)
To: Ralph Blach; +Cc: linuxppc-embedded
Ralph Blach wrote:
> This will NOT work because for Level interrupts, the ISR will cannot be
> reset until
> the interrupting source is cleared.
It works for Level interrupts on the 8xx and 8260.......
> The ack to reset the ISR for interrupt must go in the
>
> ppcxxx_aic_enable
So, put it there. All of these functions should be unique to
the 405GP interrupt controller. You are free to implement this
as you wish.
-- Dan
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: error in assumptions in the handling of interrupts.
2000-07-28 15:13 ` Dan Malek
@ 2000-07-28 17:30 ` Frank Rowand
0 siblings, 0 replies; 3+ messages in thread
From: Frank Rowand @ 2000-07-28 17:30 UTC (permalink / raw)
To: Dan Malek; +Cc: Ralph Blach, linuxppc-embedded
Dan Malek wrote:
>
> Ralph Blach wrote:
>
> > This will NOT work because for Level interrupts, the ISR will cannot be
> > reset until
> > the interrupting source is cleared.
>
> It works for Level interrupts on the 8xx and 8260.......
>
> > The ack to reset the ISR for interrupt must go in the
> >
> > ppcxxx_aic_enable
>
> So, put it there. All of these functions should be unique to
> the 405GP interrupt controller. You are free to implement this
> as you wish.
>
> -- Dan
>
I'll take care of the problem in the 405gp version of these functions, but there
are also 403 specific versions of the functions. I've seen various people on this
mailing list posting about 4xx processors (other than 405), but I haven't figured
out if there is anyone who is at the center of 401 and/or 403 development and
haven't found the info in the various FAQs yet. Is there any such person?
Thanks,
-Frank
--
Frank Rowand <frank_rowand@mvista.com>
MontaVista Software, Inc
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
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2000-07-28 15:13 ` Dan Malek
2000-07-28 17:30 ` Frank Rowand
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