Re: PCI Buses

Re: PCI Buses

[jlquinn]

I thought the 9500/9600 had two PCI buses with 3 slots each?

Jerry Quinn


tom_gall@vnet.ibm.com@lists.linuxppc.org on 08/15/2000 02:46:15 PM
Hi *,

  Just a stupid question here for those of you that have Mac hardware. Of
all
the Mac hardware in existance right now, all Macs have at most one PCI bus
right?

  Thanks for any info!

  Regards,

  Tom


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Re: PCI Buses

[David Riley]

jlquinn@us.ibm.com wrote:

> I thought the 9500/9600 had two PCI buses with 3 slots each?
>
> Jerry Quinn
>

Well, the 9500/9600 have 6 PCI slots, though it's anyone's guess as to how
many are on each bus.  However, the Blue G3's and all G4's as well as the
iBook and any other computer with AGP (including the "fake AGP" fast PCI slot
on the blue G3's) have two PCI busses, since AGP is only a fast PCI bus (with
a few enhancements, but as far as Linux is concerned, it's PCI).  AGP slots
will run compatible PCI cards at 66MHz (though there are certain keys which
prevent insertion unless the card is compatible).  A notable example is
3Dfx's Voodoo2 1000 card (and several other brands) which allow a 66 MHz bus.

On a side note, does anyone know if Linux properly supports the 64-bit PCI
slots in the Blue G3's and G4's?  The only cards I know of that use them are
several SCSI cards and TotalImpact cards.

Thanks,
    David


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Re: PCI Buses

[Gabriel Paubert]

On Tue, 15 Aug 2000, David Riley wrote:

> On a side note, does anyone know if Linux properly supports the 64-bit PCI
> slots in the Blue G3's and G4's?  The only cards I know of that use them are
> several SCSI cards and TotalImpact cards.

>From a software point of view 64 bit PCI is indistinguishable from 32 bit.
Actually MVME boards have a 64 bit PCI host bridge, although only the VME
bridge (Tundra's Universe) is a 64 bit device. The software just does not
care. PIO transfers of 32 bit or less (in practice all on a 32 bit
processor) will use standard PCI bus protocol for reads; writes may be
merged under some conditions by the processor or the host bridge as
explained for example in the PPC750 or CPC710 (IBM) doc. Still these
operations are often short (with the exception of graphics adapter memory
accesses) and the benefit of 64 bit transfers versus a short burst of 32
bit transfers is minimal.

DMA operations on the other hand benefit a lot from 64 bit transfers,
since well designed adapters will have large FIFOs and generate bursts of
several tens of transfers at which point the overhead of setting up the
operation becomes small. In practice this almost halves the bus
utilization.


	Regards,
	Gabriel


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PCI Buses

[tom_gall]

Hi *,

  Just a stupid question here for those of you that have Mac hardware. Of all
the Mac hardware in existance right now, all Macs have at most one PCI bus
right?

  Thanks for any info!

  Regards,

  Tom

--
Tom Gall - PowerPC Linux Team    "Where's the ka-boom? There was
Linux Technology Center           supposed to be an earth
(w) tom_gall@vnet.ibm.com         shattering ka-boom!"
(w) 507-253-4558                 -- Marvin Martian
(h) tgall@uswest.net
http://oss.software.ibm.com/developerworks/opensource/linux

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Re: PCI Buses

[Ani Joshi]

Most Macs have 1 bus (almost all from the OldWorld series), but some 9x00
have 2 busses.  Also recent Apple G4's have 3.


ani




On Tue, 15 Aug 2000 tom_gall@vnet.ibm.com wrote:

>
> Hi *,
>
>   Just a stupid question here for those of you that have Mac hardware. Of all
> the Mac hardware in existance right now, all Macs have at most one PCI bus
> right?
>
>   Thanks for any info!
>
>   Regards,
>
>   Tom
>
> --
> Tom Gall - PowerPC Linux Team    "Where's the ka-boom? There was
> Linux Technology Center           supposed to be an earth
> (w) tom_gall@vnet.ibm.com         shattering ka-boom!"
> (w) 507-253-4558                 -- Marvin Martian
> (h) tgall@uswest.net
> http://oss.software.ibm.com/developerworks/opensource/linux
>
>


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Re: PCI Buses

[Michel Lanners]

Hi Tom,

On  15 Aug, this message from tom_gall@vnet.ibm.com echoed through cyberspace:
>   Just a stupid question here for those of you that have Mac hardware. Of all
> the Mac hardware in existance right now, all Macs have at most one PCI bus
> right?

Wrong :-)

As has been said before, the 9x00 have two PCI busses on two identical
bandit host bridges.

Also, the 73/75/76/85/8600 have an additional bus called VCI by Apple,
for accessing video in/out hardware, that behaves exactly like a PCI
bus.

Then, there are newer Macs, with those based on UniNorth having three
PCI buses (AGP counted in).

Michel

-------------------------------------------------------------------------
Michel Lanners                 |  " Read Philosophy.  Study Art.
23, Rue Paul Henkes            |    Ask Questions.  Make Mistakes.
L-1710 Luxembourg              |
email   mlan@cpu.lu            |
http://www.cpu.lu/~mlan        |                     Learn Always. "


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Re: PCI Buses

[tom_gall]

Michel Lanners wrote:
>
> Hi Tom,
>
> On  15 Aug, this message from tom_gall@vnet.ibm.com echoed through cyberspace:
> >   Just a stupid question here for those of you that have Mac hardware. Of all
> > the Mac hardware in existance right now, all Macs have at most one PCI bus
> > right?

Hi All,

  I thank you much for the information. It took me a little bit but as I've been
looking at the PCI code I ran across the pmac PCI implementation which
definately has support for more than one PCI bus.

  Where I'm coming from is getting the same thing working on IBM PowerPC
hardware for multiple pythons... fun fun fun...

  Thanks again!


> Wrong :-)
>
> As has been said before, the 9x00 have two PCI busses on two identical
> bandit host bridges.
>
> Also, the 73/75/76/85/8600 have an additional bus called VCI by Apple,
> for accessing video in/out hardware, that behaves exactly like a PCI
> bus.
>
> Then, there are newer Macs, with those based on UniNorth having three
> PCI buses (AGP counted in).

It's definately interesting to hear that AGP is really just another PCI... or at
least treated that way. Being PCI/AGP stupid I appreciate the info... if it's
just another "PCI" of sorts, doesn't that have performance implications or is
that addressed really by the hardware implementation as apposed to the Linux
side of things?

Regards,

--
Tom Gall - PowerPC Linux Team    "Where's the ka-boom? There was
Linux Technology Center           supposed to be an earth
(w) tom_gall@vnet.ibm.com         shattering ka-boom!"
(w) 507-253-4558                 -- Marvin Martian
(h) tgall@uswest.net
http://oss.software.ibm.com/developerworks/opensource/linux

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Re: PCI Buses

[David Riley]

tom_gall@vnet.ibm.com wrote:

> It's definately interesting to hear that AGP is really just another PCI... or at
> least treated that way. Being PCI/AGP stupid I appreciate the info... if it's
> just another "PCI" of sorts, doesn't that have performance implications or is
> that addressed really by the hardware implementation as apposed to the Linux
> side of things?

It really is just another PCI (there is a 66 MHz PCI specification, and AGP uses
it), though there are improvements made (for example, sidebanding, which gives us
the 2x and 4x modes).  Additionally, it's adapted on the Intel side of things for
"write combining" (if anyone comes up with an exact definition of how that works,
please let me know).  I'm not sure what you mean by performance implications, but
PCI isn't a horrible bus to start with...


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Re: PCI Buses

[Geert Uytterhoeven]

On Tue, 15 Aug 2000, David Riley wrote:
> tom_gall@vnet.ibm.com wrote:
> > It's definately interesting to hear that AGP is really just another PCI... or at
> > least treated that way. Being PCI/AGP stupid I appreciate the info... if it's
> > just another "PCI" of sorts, doesn't that have performance implications or is
> > that addressed really by the hardware implementation as apposed to the Linux
> > side of things?
>
> It really is just another PCI (there is a 66 MHz PCI specification, and AGP uses
> it), though there are improvements made (for example, sidebanding, which gives us
> the 2x and 4x modes).  Additionally, it's adapted on the Intel side of things for
> "write combining" (if anyone comes up with an exact definition of how that works,
> please let me know).  I'm not sure what you mean by performance implications, but
> PCI isn't a horrible bus to start with...

`write combining' means that the PCI bridge will buffer successive writes to
successive addresses and combine them into one burst of writes. Since burst
writes are more efficient than individual writes (which require an address
setup operation for every write), this is a win. Of course you cannot always
use write combining (think about register writes), but for frame buffer
accesses it's nice.

BTW, if you look at the specs for the host bridge IBM used in the (dead?) POP
design, you'll see that it actually has 2 PCI buses: one at 33 MHz and one at
66 MHz. The 66 MHz can be used as an AGP bus as well, as is done in the POP
design.

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds


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Re: PCI Buses

[Matt Porter]

On Tue, Aug 15, 2000 at 11:16:14PM +0000, tom_gall@vnet.ibm.com wrote:
>
> Michel Lanners wrote:
> >
> > Hi Tom,
> >
> > On  15 Aug, this message from tom_gall@vnet.ibm.com echoed through cyberspace:
> > >   Just a stupid question here for those of you that have Mac hardware. Of all
> > > the Mac hardware in existance right now, all Macs have at most one PCI bus
> > > right?
>
> Hi All,
>
>   I thank you much for the information. It took me a little bit but as I've been
> looking at the PCI code I ran across the pmac PCI implementation which
> definately has support for more than one PCI bus.
>
>   Where I'm coming from is getting the same thing working on IBM PowerPC
> hardware for multiple pythons... fun fun fun...

Do you mean two separate physical buses like on the CPC710 PHB?  If so,
then check out the SBS K2 LSP code in MontaVista CDK1.2 release
(ftp.mvista.com).  There's some extra layering in their to allow
for kernel resident PCI autoconfiguration before the generic bus scan
as well as transparent handling of config space accesses via the different
CFGA/CFGD addresses.

--
Matt Porter
MontaVista Software, Inc.
mporter@mvista.com

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