From: Adrian Cox <apc@agelectronics.co.uk>
To: Gabriel Paubert <paubert@iram.es>
Cc: mlan@cpu.lu, linuxppc-dev@lists.linuxppc.org
Subject: Re: PATCH: improved processor config for G3s
Date: Mon, 04 Sep 2000 11:34:58 +0100 [thread overview]
Message-ID: <39B37AD2.120E2DE7@agelectronics.co.uk> (raw)
In-Reply-To: Pine.HPX.4.10.10009041137010.15978-100000@gra-ux1.iram.es
Gabriel Paubert wrote:
> A rule of thumb is the following: fully SMP capable processors broadcast
> eieio (and tlbie for that matter), others do not at least by default. On
> an UP 750 (SMP 750 are an aberration in any case because of TLB issues),
> I'd bet that it is more efficient to let the processor perform store
> gathering when it can (an eieio between both stores will prevent it) and
> to disable both ABE in the processor and store gathering in the bridge.
> This will result in lower processor bus utilization.
Remember that the processor store gathering is only capable of turning
two 32-bit writes to uncached, nonguarded space into one 64-bit write.
The bridge store gathering converts an arbitrary sequence of sequential
writes into a PCI burst.
The bridge store gathering should be able to produce far more IO
improvement, and still works if the guard bit is set on the address
space.
I should have done a set of MPC107 experiments by the start of October,
and I'll know for sure then.
- Adrian Cox, AG Electronics
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2000-09-04 10:34 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2000-09-03 13:03 PATCH: improved processor config for G3s Michel Lanners
2000-09-03 13:43 ` Benjamin Herrenschmidt
2000-09-04 9:48 ` Gabriel Paubert
2000-09-04 10:34 ` Adrian Cox [this message]
2000-09-04 10:54 ` Benjamin Herrenschmidt
2000-09-05 9:49 ` Gabriel Paubert
2000-09-05 10:50 ` Benjamin Herrenschmidt
2000-09-05 11:06 ` Gabriel Paubert
2000-09-05 11:32 ` Adrian Cox
2000-09-04 17:51 ` Michel Lanners
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