flying blind with BATs

flying blind with BATs

[Tim Montgomery]

hello,

I am trying to get the ppc kernel loaded on a 750-based embedded board,
and I've got an ultra-basic bootloader (the board is not PReP or
CHRP-compliant), but I believe I am having trouble with the BAT
mappings.

I have the BATs configure (by the bootloader) such that 0xc0000000
(virtual) is mapped to 0x00000000 (phys SDRAM base), but after
the image is decompressed (to the virtual addr), I get garbage when
I do a dump at 0xc0000000 (i.e. the kernel isn't there.)

I am executing the bootloader itself out of a region well above
(4MB) the kernel space.

Before I spend too much time reinventing the wheel (and beating my
head against the wall), I was curious if there was a 7xx-based
bootloader out there that I could modify to fit my needs.

Any other pointers/tips regarding machine state required on a 750
prior to jumping to the kernel would also be appreciated.

Regards,
Tim

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Re: flying blind with BATs

[Adrian Cox]

Tim Montgomery wrote:

> I have the BATs configure (by the bootloader) such that 0xc0000000
> (virtual) is mapped to 0x00000000 (phys SDRAM base), but after
> the image is decompressed (to the virtual addr), I get garbage when
> I do a dump at 0xc0000000 (i.e. the kernel isn't there.)

My trick is just to load the ELF file to physical address 0. The elf
file format is easy enough to decode (mine is about 60 lines of C, and
I'll post it if there's interest). Then, I load r3 with a value to
indicate machine type ('TPE3' or 'TPE4'), and jump to the start of the
kernel turning off the cache and MMU.

Important things to note are:
1) Flush the caches over the region you've just loaded before fiddling
with MMU and cache settings.

Here's the section of my bootloader - r3 is the kernel entry point
(physical address) and r4 is 'TPE3':
ppc_run_executable:
        mtspr   SRR0, r3
        mr      3, 4
        mfspr   9, HID0
        li      10, HID0_DCE
        andc    9, 9, 10
        mtspr   HID0, 9
        sync
        mfmsr   9
        li      10, MSR_DR | MSR_IR
        andc    9, 9, 10
        mtspr   SRR1, 9
        sync
        rfi

- Adrian Cox, AG Electronics

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