ethernet on fads850sar board?

ethernet on fads850sar board?

[Dan A. Dickey]

Hi,
this is a shot in the dark - but does anyone have
ethernet working on the fads850sar board, or any fads board?
Could I please see the code...  I'm working with the ppcboot
project, but can't seem to get this going on my fads board,
and don't really understand why.  The hub I'm connecting to
shows activity when I send a packet, but ethereal on my
also connected to the hub linux machine doesn't show anything
coming in.  After sending the packet, the status of the TxBD
is pretty much what I'd expect - 0x6c00.
Any ideas?
(And why do the baud rate generators that feed the ethernet
 clocks need to run at 2Mhz?)
	-Dan

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Re: ethernet on fads850sar board?

[Dan Malek]

"Dan A. Dickey" wrote:

> Any ideas?

Make sure the GP I/O pins are configured properly to be SCC2 Ethernet
control/status lines.  Make sure the BCSR bits enable and properly
configure the PHY (half/full duplex, loopback, etc.).

> (And why do the baud rate generators that feed the ethernet
>  clocks need to run at 2Mhz?)

Ummm, no.....The PHY provides the clocks, they are inputs to port.
I don't know why an external clock would be set to that value.

	-- Dan

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Re: ethernet on fads850sar board?

[Dan A. Dickey]

Dan Malek wrote:
>
> "Dan A. Dickey" wrote:
>
> > Any ideas?
>
> Make sure the GP I/O pins are configured properly to be SCC2 Ethernet
> control/status lines.  Make sure the BCSR bits enable and properly
> configure the PHY (half/full duplex, loopback, etc.).

I've been over them about three times already.  But I can certainly
check again.

> > (And why do the baud rate generators that feed the ethernet
> >  clocks need to run at 2Mhz?)
>
> Ummm, no.....The PHY provides the clocks, they are inputs to port.
> I don't know why an external clock would be set to that value.

The only way that I could get a packet to go (otherwise I got a
TX Timeout) was by clocking SCC2 to one or two of the Baud Rate
Generators.  I've tried CLK4, and CLK1+CLK3.  It didn't work.
By this, I mean that right now I'm doing a:
    immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
Where SICR_ENET_CLKRT is:
#define SICR_ENET_CLKRT ((uint)0x00001300)  /* RCLK-BRG3, TCLK-BRG4 */

Otherwise, where does the RCLK and TCLK come from or go to?
(And what speed *should* they be running at?)
Is there something more that I can read to get an understanding
of what is going on here?

Thank you for your help.
	-Dan

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Re: ethernet on fads850sar board?

[Dan A. Dickey]

"Dan A. Dickey" wrote:
> Dan Malek wrote:
> >
> > "Dan A. Dickey" wrote:
> >
> > > Any ideas?
> >
> > Make sure the GP I/O pins are configured properly to be SCC2 Ethernet
> > control/status lines.  Make sure the BCSR bits enable and properly
> > configure the PHY (half/full duplex, loopback, etc.).
>
> I've been over them about three times already.  But I can certainly
> check again.
>
> > > (And why do the baud rate generators that feed the ethernet
> > >  clocks need to run at 2Mhz?)
> >
> > Ummm, no.....The PHY provides the clocks, they are inputs to port.
> > I don't know why an external clock would be set to that value.

Dan, Thank You!
This cyptic comment (for me anyways) was the key to getting
ethernet going on my fads850 board.  I now understand the ethernet
clocks, and the parallel I/O ports much better than I did a few
days ago.

And yes indeed, the baud rate generators are not needed at all;
so now I'm leaving them alone all together.

> The only way that I could get a packet to go (otherwise I got a
> TX Timeout) was by clocking SCC2 to one or two of the Baud Rate
> Generators.  I've tried CLK4, and CLK1+CLK3.  It didn't work.
> By this, I mean that right now I'm doing a:
>     immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
> Where SICR_ENET_CLKRT is:
> #define SICR_ENET_CLKRT ((uint)0x00001300)  /* RCLK-BRG3, TCLK-BRG4 */

What I needed to do and ended up doing was using CLK2 for the RCLK, and
CLK4 for the TCLK; thusly:
#define SICR_ENET_CLKRT    ((uint)0x00002f00)      /* RCLK-CLK2,
TCLK-CLK4 */

Thanks again for everyones help.
	-Dan

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