From: Dan Malek <dan@mvista.com>
To: frowand@mvista.com
Cc: linuxppc-dev <linuxppc-dev@lists.linuxppc.org>
Subject: Re: kernel mapping
Date: Wed, 17 Jan 2001 02:02:54 -0500 [thread overview]
Message-ID: <3A65439E.85B8CD9F@mvista.com> (raw)
In-Reply-To: 3A64E1AA.7F955CCA@mvista.com
Frank Rowand wrote:
> The 405 core (and thus the many processors based on it) has a 64 entry
> tlb. While debugging via a JTAG debugger I have observed that the
> tlb very quickly gets filled with entries for the current context.
Well, that's because we force it to do that. Programs that have
a huge working set and run for an extended period will fill the
TLB. Programs with small working sets will not if we actually
use the contexts properly, but we don't. The way contexts are
used today, it is effectively flushing the TLB on every switch.
We do the same thing with VSIDs on the "bigger" processors, and
this isn't right either. The Linux VM properly manages memory
contexts, and we should extend this into the PowerPC specific
software.
I have an LRU context algorithm for the 8xx, and I want to extend
this into the 4xx and even the other processors. The idea is right,
but I need something that will scale beyond the small 16 contexts
of the 8xx. I just don't have that yet.
-- Dan
--
I like MMUs because I don't have a real life.
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
prev parent reply other threads:[~2001-01-17 7:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-01-15 23:13 kernel mapping Dan Malek
2001-01-16 3:07 ` Frank Rowand
2001-01-16 3:55 ` Dan Malek
2001-01-16 11:37 ` Ralph Blach
2001-01-16 16:50 ` Dan Malek
2001-01-16 17:10 ` Ralph Blach
2001-01-16 17:47 ` David Edelsohn
2001-01-16 21:57 ` Dan Malek
2001-01-17 10:51 ` Gabriel Paubert
2001-01-17 17:45 ` David Edelsohn
2001-01-16 19:56 ` Frank Rowand
2001-01-16 22:13 ` Dan Malek
2001-01-17 0:04 ` Frank Rowand
2001-01-17 7:02 ` Dan Malek [this message]
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