mtmsr...

mtmsr...

[Prasad, Siva]

Hello,

My zImage hangs immediately after executing the 'mtmsr' instruction in the
arch/ppc/boot/head.S file.

li    r3, 0
mtmsr r3
isync

This is in the very beginning of the zImage, where it uncompresses the
actual image. Can some one help me out.

Thanks in advance.
-- Siva

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Re: mtmsr...

[Tom Rini]

On Tue, Sep 25, 2001 at 06:53:19PM -0700, Prasad, Siva wrote:
>

> My zImage hangs immediately after executing the 'mtmsr' instruction in the
> arch/ppc/boot/head.S file.
>
> li    r3, 0
> mtmsr r3
> isync
>
> This is in the very beginning of the zImage, where it uncompresses the
> actual image. Can some one help me out.

What machine? What kernel?  From where?

--
Tom Rini (TR1265)
http://gate.crashing.org/~trini/

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RE: mtmsr...

[Prasad, Siva]

PowerPC 750 on a custom board.
I tried both the bitkeeper source (2.4.10-pre11) and also HartHat Linux CDK
1.2 version (kernel 2.2.14). Same problem in both the kernels.

I really appreciate any kind of help on this as I am clueless.

Thanks in advance.

-- Siva


> -----Original Message-----
> From: Tom Rini [mailto:trini@kernel.crashing.org]
> Sent: Tuesday, September 25, 2001 7:10 PM
> To: Prasad, Siva
> Cc: linuxppc-embedded@lists.linuxppc.org
> Subject: Re: mtmsr...
>
>
> On Tue, Sep 25, 2001 at 06:53:19PM -0700, Prasad, Siva wrote:
> >
>
> > My zImage hangs immediately after executing the 'mtmsr'
> instruction in the
> > arch/ppc/boot/head.S file.
> >
> > li    r3, 0
> > mtmsr r3
> > isync
> >
> > This is in the very beginning of the zImage, where it
> uncompresses the
> > actual image. Can some one help me out.
>
> What machine? What kernel?  From where?
>
> --
> Tom Rini (TR1265)
> http://gate.crashing.org/~trini/
>

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mtmsr...

[Matt Porter]

On Wed, Sep 26, 2001 at 03:46:55PM -0700, Prasad, Siva wrote:
>
> 'PowerBoot' is the firmware I am using.
>
> I preferred to use 2.2.14 because, it has PowerCore option, where I can use
> 750  with minimal changes.
>
> I am not making any calls to firmware after that. This 'mtmsr' instruction
> is third instruction and it hangs with out finishing. What might be the
> problem that I have to fix to get this working.

Force's PowerBoot doesn't properly clean up caches before handing
control over to an external program.  You are probably having
cache problems that we have run into on some COTS Force boards.
I had to disable, flush, reenable L1 icache on the 680/G4, for
example.  linuxppc_2_4_devel's simple bootloader has a specific
CONFIG_PCORE option for this, in fact.

--
Matt Porter
MontaVista Software, Inc.
mporter@mvista.com

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mtmsr...

[Tom Rini]

On Wed, Sep 26, 2001 at 09:40:31AM -0700, Prasad, Siva wrote:

> PowerPC 750 on a custom board.
> I tried both the bitkeeper source (2.4.10-pre11) and also HartHat Linux CDK
> 1.2 version (kernel 2.2.14). Same problem in both the kernels.

Well, both of those sources are very different.  Are you running this
board in 'PReP' mode?  Your own firmware or what?  Anyhow, if you're making
any calls back to the firmware later on, you must not mess w/ the MSR value.

--
Tom Rini (TR1265)
http://gate.crashing.org/~trini/

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

RE: mtmsr...

[Prasad, Siva]

'PowerBoot' is the firmware I am using.

I preferred to use 2.2.14 because, it has PowerCore option, where I can use
750  with minimal changes.

I am not making any calls to firmware after that. This 'mtmsr' instruction
is third instruction and it hangs with out finishing. What might be the
problem that I have to fix to get this working.

-- Siva


> -----Original Message-----
> From: Tom Rini [mailto:trini@kernel.crashing.org]
> Sent: Wednesday, September 26, 2001 3:43 PM
> To: Prasad, Siva
> Cc: linuxppc-embedded@lists.linuxppc.org
> Subject: Re: mtmsr...
>
>
> On Wed, Sep 26, 2001 at 09:40:31AM -0700, Prasad, Siva wrote:
>
> > PowerPC 750 on a custom board.
> > I tried both the bitkeeper source (2.4.10-pre11) and also
> HartHat Linux CDK
> > 1.2 version (kernel 2.2.14). Same problem in both the kernels.
>
> Well, both of those sources are very different.  Are you running this
> board in 'PReP' mode?  Your own firmware or what?  Anyhow, if
> you're making
> any calls back to the firmware later on, you must not mess w/
> the MSR value.
>
> --
> Tom Rini (TR1265)
> http://gate.crashing.org/~trini/
>

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mtmsr...

[Mark A. Greer]

"Prasad, Siva" wrote:

> 'PowerBoot' is the firmware I am using.
>
> I preferred to use 2.2.14 because, it has PowerCore option, where I can use
> 750  with minimal changes.

Siva, my guess is that it is one of two things:
a) The value you are putting into the msr is bad and making it hang (like
turning on the mmu)
b) Its a stale cache problem and the instructions you *think* you are
executing aren't really what the processor is executing.

Mark


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Re: mtmsr...

[Dan Malek]

Matt Porter wrote:

> Force's PowerBoot doesn't properly clean up caches before handing
> control over to an external program.  You are probably having
> cache problems that we have run into on some COTS Force boards.
> I had to disable, flush, reenable L1 icache on the 680/G4, for
> example.

So, you are really running on luck then.  When you disable the
cache, you are just fortunate that the necessary instructions
to do the remainder of the work just happen to be in main memory,
and that the cache was somehow implicitly invalidated so the ones
you need to get to this point aren't stale in the cache.  Are
you really sure the caches aren't cleaned up properly and this
sequence of operations isn't masking some other problem?


	-- Dan

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Re: mtmsr...

[Matt Porter]

On Wed, Sep 26, 2001 at 08:47:12PM -0400, Dan Malek wrote:
> Matt Porter wrote:
>
> > Force's PowerBoot doesn't properly clean up caches before handing
> > control over to an external program.  You are probably having
> > cache problems that we have run into on some COTS Force boards.
> > I had to disable, flush, reenable L1 icache on the 680/G4, for
> > example.
>
> So, you are really running on luck then.  When you disable the

Absolutely, we are running on luck.

> cache, you are just fortunate that the necessary instructions
> to do the remainder of the work just happen to be in main memory,
> and that the cache was somehow implicitly invalidated so the ones
> you need to get to this point aren't stale in the cache.  Are
> you really sure the caches aren't cleaned up properly and this
> sequence of operations isn't masking some other problem?

I understand it's dangerous but it did limp around whatever the
root problem is.  It could be masking another problem...this
is a problem awaiting someone with time to understand it.

--
Matt Porter
MontaVista Software, Inc.
mporter@mvista.com

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