From: Dan Malek <dan@mvista.com>
To: Matt Porter <mporter@mvista.com>
Cc: "Prasad, Siva" <Siva.Prasad@smartm.com>,
"'Tom Rini'" <trini@kernel.crashing.org>,
linuxppc-embedded@lists.linuxppc.org
Subject: Re: mtmsr...
Date: Wed, 26 Sep 2001 20:47:12 -0400 [thread overview]
Message-ID: <3BB27710.68CBE18A@mvista.com> (raw)
In-Reply-To: 20010926125756.A28204@cx258813-a.chnd1.az.home.com
Matt Porter wrote:
> Force's PowerBoot doesn't properly clean up caches before handing
> control over to an external program. You are probably having
> cache problems that we have run into on some COTS Force boards.
> I had to disable, flush, reenable L1 icache on the 680/G4, for
> example.
So, you are really running on luck then. When you disable the
cache, you are just fortunate that the necessary instructions
to do the remainder of the work just happen to be in main memory,
and that the cache was somehow implicitly invalidated so the ones
you need to get to this point aren't stale in the cache. Are
you really sure the caches aren't cleaned up properly and this
sequence of operations isn't masking some other problem?
-- Dan
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2001-09-27 0:47 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-09-26 22:46 mtmsr Prasad, Siva
2001-09-26 19:57 ` mtmsr Matt Porter
2001-09-27 0:47 ` Dan Malek [this message]
2001-09-27 1:20 ` mtmsr Matt Porter
2001-09-26 23:33 ` mtmsr Mark A. Greer
-- strict thread matches above, loose matches on Subject: below --
2001-09-26 16:40 mtmsr Prasad, Siva
2001-09-26 22:43 ` mtmsr Tom Rini
2001-09-26 1:53 mtmsr Prasad, Siva
2001-09-26 2:09 ` mtmsr Tom Rini
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