PPC 405 Register Model

PPC 405 Register Model

[Jim Duey]

I'm needing to do some inline assembly for the Walnut board running MVista's
Hard Hat Linux and I'm concerned about clobbering registers.  Can someone
point me to docs or source code that describes the register usage of HHL on
the 405GP?

Thanks,

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Re: PPC 405 Register Model

[Jerry Van Baren]

It's in the specs ABI/EABI ([Embedded] Application Binary Interface).  All
compilers I have run across support EABI by default.
   http://www.esofta.com/softspecs.html

gvb


At 11:58 AM 10/30/01 -0600, you wrote:

>I'm needing to do some inline assembly for the Walnut board running MVista's
>Hard Hat Linux and I'm concerned about clobbering registers.  Can someone
>point me to docs or source code that describes the register usage of HHL on
>the 405GP?
>
>Thanks,
>


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Re: PPC 405 Register Model

[Frank Rowand]

Jim Duey wrote:
>
> I'm needing to do some inline assembly for the Walnut board running MVista's
> Hard Hat Linux and I'm concerned about clobbering registers.  Can someone
> point me to docs or source code that describes the register usage of HHL on
> the 405GP?

If you use variable names instead of hard coding register numbers you
don't have to worry about clobbering registers.  For example, look
at include/asm-ppc/atomic.h and you can find documentation of inline
assembly at:

  http://gcc.gnu.org/onlinedocs/gcc-2.95.2/gcc_4.html#SEC93

-Frank
--
Frank Rowand <frank_rowand@mvista.com>
MontaVista Software, Inc

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Re: PPC 405 Register Model

[Scott Anderson]

Frank Rowand wrote:
>
> Jim Duey wrote:
> >
> > I'm needing to do some inline assembly for the Walnut board running MVista's
> > Hard Hat Linux and I'm concerned about clobbering registers.  Can someone
> > point me to docs or source code that describes the register usage of HHL on
> > the 405GP?
>
> If you use variable names instead of hard coding register numbers you
> don't have to worry about clobbering registers.

FYI, I've seen gcc pass r0 as the register that a variable gets stored
in.  Because some PPC instructions treat r0 as a literal zero instead of
the value in r0, this can be bad.  To work around this, you just need
to tell gcc that the asm uses r0 and it won't pass you a parameter in
it.  Here's an example chunk of code:


	/* Get the Time Base.  Make sure that r0 is declared as used;
	 * otherwise it can be passed to me as %0 which doesn't work
	 * very well with stw.
	 */
	asm volatile ("0:; mftbu 3; mftb 4; mftbu 0; cmpw 3,0; bne 0b; "
		      "stw 3,0(%0); stw 4,4(%0)"
		      :: "r" (&tb): "r3", "r4", "r0");

The "r0" at the tail end of the asm tells gcc that r0 is used.

    Scott Anderson
    scott_anderson@mvista.com   MontaVista Software Inc.
    (408)328-9214               1237 East Arques Ave.
    http://www.mvista.com       Sunnyvale, CA  94085

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Re: PPC 405 Register Model

[Peter Barada]

>FYI, I've seen gcc pass r0 as the register that a variable gets stored
>in.  Because some PPC instructions treat r0 as a literal zero instead of
>the value in r0, this can be bad.  To work around this, you just need
>to tell gcc that the asm uses r0 and it won't pass you a parameter in
>it.  Here's an example chunk of code:
>
>
>	/* Get the Time Base.  Make sure that r0 is declared as used;
>	 * otherwise it can be passed to me as %0 which doesn't work
>	 * very well with stw.
>	 */
>	asm volatile ("0:; mftbu 3; mftb 4; mftbu 0; cmpw 3,0; bne 0b; "
>		      "stw 3,0(%0); stw 4,4(%0)"
>		      :: "r" (&tb): "r3", "r4", "r0");
>
>The "r0" at the tail end of the asm tells gcc that r0 is used.

1) You use r0 as a temporary value, so you have to tell gcc that
   r0 is being clobbered.

2) You specified that &tb can be placed in a "r" register class
   which includes r0.  If you change the register class to "b", then
   &tb would select any register that can be used as a base address,
   which is any general register *except* r0.

3) Since you are modifying the value in memory at the address
   contained in tb, you should add "memory" to the clobber list so the
   compiler won't assume that any memory values cached in registers
   are valid.

You could rewrite this asm statement as:

{   unsigned int tmp1, tmp2, tmp3;
 asm volatile("0:; mtfbu %0; mtfb %1; mtfb %2; cmp %0,%2; bne 0b; "
    "stw %0,0(%4); stw %1,4(%4)"
     : "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
     : "b" (&tb)
     : "memory");
}

All the output operands (tmp1/2/3) need to have "=" in the descriptor
to indicate that they are output values, and also need "&" to indicate
that they can not be shared with the intput value since these are
clobbered in the asm template before the input operand is consumed.

--
Peter Barada                                   Peter.Barada@motorola.com
Wizard                                         781-852-2768 (direct)
WaveMark Solutions(wholly owned by Motorola)   781-270-0193 (fax)

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PPC 405 Register Model

[Jim Duey]

Thanks for all the responses

Jim

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