Re: PCI QSPAN2 resource conflicts

[Peter Desnoyers <pdesnoyers@chinook.com>]

I wrote:
>
> br0 = f4000001, i/o at 0xf4000000, size 128 (weird - assigned from
> bottom of range here, not top)
> br1 = f5ffff80, memory at 0xf5ffff80 size 128
>
> You can't have it both ways - 0xf5ffffxx is either I/O or memory, but
> not both.

I'm forgetting - the values in the registers are actual PCI I/O and
memory addresses, so there's no issue if they overlap.  (the physical
addresses mapped to them on the CPU side can't overlap, though) And when
I was talking about target image programming in the QSpan, I should have
been referring to the bus addresses, not the physical addresses.

However, I still get the feeling that there's something badly wrong with
the way you've got your base registers mapped on the two devices, plus
your device is just plain turned off.

--
.....................................................................
 Peter Desnoyers            (781) 457-1165   pdesnoyers@chinook.com
 Chinook Communications     (617) 661-1979   pjd@fred.cambridge.ma.us
 100 Hayden Ave, Lexington MA 02421

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