PPC405gp enet Soft Reset

PPC405gp enet Soft Reset

[andrew may]

I seem to be having a problem with the soft reset of EMAC
mode register when I have no ethernet connection to by phy.

After this code in init_ppc405_enet(void) the SRST bit does
not clear until after I stick in a cable.

		/* Reset the EMAC */
		emacp->em0mr0 = EMAC_M0_SRST;
		eieio();
		for (delay = 0; delay < 1000; delay++) ;
		emacp->em0mr0 = emacp->em0mr0 & ~EMAC_M0_SRST;
		eieio();
                printk( KERN_INFO "em0mr0 %08x", emacp->em0mr0 );


This causes problems in find_phy, since phy_reg never gets set to
a value and read_mdio fails.

I have a Rev E chip, but since I always booted over the net with the
Walnut board I don't think I even tried to boot without an ethernet
connection.

Just checking to see if anyone else has noticed what their 405gp does
when it doesn't have a connection during the linux boot.

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Re: PPC405gp enet Soft Reset

[Stefan Roese]

Andrew

> I seem to be having a problem with the soft reset of EMAC
> mode register when I have no ethernet connection to by phy.

We have the same problem (CPCI-405 with Intel LXT971 PHY).

> After this code in init_ppc405_enet(void) the SRST bit does
> not clear until after I stick in a cable.

See Chapter 19.7.1 in PPC405GP User Manual (EMAC0_MR0):

"Both PHY clocks, PHYTxClk and PHYRxClk, must be active prior to requesting
a soft reset through EMAC0_MR0[SRST]. If the PHY clocks are inactive, the
soft reset never completes, even if the clocks subsequently become
active..."

It seems that we can't reset and setup the EMAC correctly without cable
connected (no cable == no PHY clock!). So what do we do when this occurs?
Disable the driver?

Stefan Roese.


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Re: PPC405gp enet Soft Reset

[Armin]

andrew may wrote:

> On Fri, Feb 08, 2002 at 11:03:59AM +0100, Stefan Roese wrote:
>
>>Andrew
>>
>>
>>>I seem to be having a problem with the soft reset of EMAC
>>>mode register when I have no ethernet connection to by phy.
>>>
>>We have the same problem (CPCI-405 with Intel LXT971 PHY).
>>
>
> It is good to see that the problem is known.
>
>
>>>After this code in init_ppc405_enet(void) the SRST bit does
>>>not clear until after I stick in a cable.
>>>
>>See Chapter 19.7.1 in PPC405GP User Manual (EMAC0_MR0):
>>
>
> The prelim hard copies I have been looking at failed to mention
> the clocks need to be active, but I did check the pdf and it is
> in there, so I guees I will try to look more at the soft copy these
> days.
>
>
>>It seems that we can't reset and setup the EMAC correctly without cable
>>connected (no cable == no PHY clock!). So what do we do when this occurs?
>>Disable the driver?
>>
>
> Your joking right? To do that is less than a 10 line hack, that I had to do
> to stop the driver from doing a panic or crashing, but I would not feel
> good about sending that as a patch. The driver needs to be able to handle
> this, but it will take some rework and it would be nice to know if there
> is really a reason to do the SoftReset before probing the phy.
>
>
>
>

Andrew & Stefan,

The softrest could probably be removed from the _init.  its dup'd in _open.



--armin


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Re: PPC405gp enet Soft Reset

[andrew may]

On Fri, Feb 08, 2002 at 11:03:59AM +0100, Stefan Roese wrote:
> Andrew
>
> > I seem to be having a problem with the soft reset of EMAC
> > mode register when I have no ethernet connection to by phy.
>
> We have the same problem (CPCI-405 with Intel LXT971 PHY).

It is good to see that the problem is known.

> > After this code in init_ppc405_enet(void) the SRST bit does
> > not clear until after I stick in a cable.
>
> See Chapter 19.7.1 in PPC405GP User Manual (EMAC0_MR0):

The prelim hard copies I have been looking at failed to mention
the clocks need to be active, but I did check the pdf and it is
in there, so I guees I will try to look more at the soft copy these
days.

> It seems that we can't reset and setup the EMAC correctly without cable
> connected (no cable == no PHY clock!). So what do we do when this occurs?
> Disable the driver?

Your joking right? To do that is less than a 10 line hack, that I had to do
to stop the driver from doing a panic or crashing, but I would not feel
good about sending that as a patch. The driver needs to be able to handle
this, but it will take some rework and it would be nice to know if there
is really a reason to do the SoftReset before probing the phy.

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Re: PPC405gp enet Soft Reset

[andrew may]

On Fri, Feb 08, 2002 at 10:53:14AM +0000, Armin wrote:
> Andrew & Stefan,
>
> The softrest could probably be removed from the _init.  its dup'd in _open.

Here is another problem I have with find_phy, that it seems that mii reads to
reg 2 of a non-existent address does not return an error but a read to reg 3
does.

Here is a log from ppcboot since it is easy to test this there without doing
a kernel build. My phy is at address 0x1f.

=> mii read 0x1 2
07FF
=> mii read 0x1 3
read err 3
a2: read: EMAC_STACR=0xffffc023, i=2
Error reading from the PHY
07FF


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Re: PPC405gp enet Soft Reset

[David Müller (ELSOFT AG)]

Hi

andrew may wrote:
> On Fri, Feb 08, 2002 at 10:53:14AM +0000, Armin wrote:
>
>>Andrew & Stefan,
>>
>>The softrest could probably be removed from the _init.  its dup'd in _open.
>>
>
> Here is another problem I have with find_phy, that it seems that mii reads to
> reg 2 of a non-existent address does not return an error but a read to reg 3
> does.
>
> Here is a log from ppcboot since it is easy to test this there without doing
> a kernel build. My phy is at address 0x1f.
>
> => mii read 0x1 2
> 07FF
> => mii read 0x1 3
> read err 3
> a2: read: EMAC_STACR=0xffffc023, i=2
> Error reading from the PHY
> 07FF
>

I'm seeing this error too on our boards. But i'm not certain, if it's a
problem of the MII controller in the 405 or a problem of the LXT971.
What revision of the 405 do you have? What clock frequency your 405 run at?


Dave


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Re: PPC405gp enet Soft Reset

[andrew may]

On Mon, Feb 11, 2002 at 12:55:05PM +0100, David Müller (ELSOFT AG) wrote:
> Hi
>
> andrew may wrote:
> > Here is a log from ppcboot since it is easy to test this there without doing
> > a kernel build. My phy is at address 0x1f.
> >
> > => mii read 0x1 2
> > 07FF
> > => mii read 0x1 3
> > read err 3
> > a2: read: EMAC_STACR=0xffffc023, i=2
> > Error reading from the PHY
> > 07FF
> >
>
> I'm seeing this error too on our boards. But i'm not certain, if it's a
> problem of the MII controller in the 405 or a problem of the LXT971.
> What revision of the 405 do you have? What clock frequency your 405 run at?

Well since I have no phy at address 1 I expect to get an error, but the problem
is that I am not getting an error when the register number is even.

The phy is at address 0x1f since it was easier for our hw guy to tie all the pins
to the same thing rather than put it at low address.

It is a RevE chip running at 266Mhz, the phy is an AMD Am79C874/ Altima AC101.

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405 MII-PHY communication problem (was: Re: PPC405gp enet Soft Reset)

[David Müller (ELSOFT AG)]

Hi

andrew may wrote:
> On Mon, Feb 11, 2002 at 12:55:05PM +0100, David Müller (ELSOFT AG) wrote:
>
>>Hi
>>
>>andrew may wrote:
>>
>>>Here is a log from ppcboot since it is easy to test this there without doing
>>>a kernel build. My phy is at address 0x1f.
>>>
>>>=> mii read 0x1 2
>>>07FF
>>>=> mii read 0x1 3
>>>read err 3
>>>a2: read: EMAC_STACR=0xffffc023, i=2
>>>Error reading from the PHY
>>>07FF
>>>
>>>
>>I'm seeing this error too on our boards. But i'm not certain, if it's a
>>problem of the MII controller in the 405 or a problem of the LXT971.
>>What revision of the 405 do you have? What clock frequency your 405 run at?
>>
>
> Well since I have no phy at address 1 I expect to get an error, but the problem
> is that I am not getting an error when the register number is even.
>
> The phy is at address 0x1f since it was easier for our hw guy to tie all the pins
> to the same thing rather than put it at low address.
>
> It is a RevE chip running at 266Mhz, the phy is an AMD Am79C874/ Altima AC101.
>
>

Our board is also a PPC405GP Rev E processor running @ 266MHz. Attached
to the MII port is an Intel LXT971ALE PHY chip @ address #1.

There i see the same error as you are describing (even-numbered PHY
registers give no error):

=> mii info
read err 3
a2: read: EMAC_STACR=0xffffc003, i=2
PHY 0x01: OUI = 0x04DE, Model = 0x0E, Rev = 0x02, 100baseT, FDX
read err 3
a2: read: EMAC_STACR=0xffffc043, i=2
read err 3
a2: read: EMAC_STACR=0xffffc063, i=2
read err 3
a2: read: EMAC_STACR=0xffffc083, i=2
read err 3
a2: read: EMAC_STACR=0xffffc0a3, i=2
read err 3

=> mii read 0 0
07FF
=> mii read 0 1
read err 3
a2: read: EMAC_STACR=0xffffc001, i=2
Error reading from the PHY
07FF
=> mii read 0 2
07FF
=> mii read 0 3
read err 3
a2: read: EMAC_STACR=0xffffc003, i=2
Error reading from the PHY
07FF
=> mii read 1 0
3100
=> mii read 1 1
7829
=> mii read 1 2
0013
=> mii read 1 3
78E2
=> mii read 2 0
07FF
=> mii read 2 1
read err 3
a2: read: EMAC_STACR=0xffffc041, i=2
Error reading from the PHY
07FF
=> mii read 2 2
07FF
=> mii read 2 3
read err 3
a2: read: EMAC_STACR=0xffffc043, i=2
Error reading from the PHY
07FF


On another custom board there is a PPC405GP Rev D processor running @
200MHz. Attached to the MII port is a Cirrus "Crystal LAN" CS8952 PHY
chip @ address #1.

With this configuration the MII controller sees a "ghost" PHY device at
adresse #0:

=> mii info
PHY 0x00: OUI = 0x0688, Model = 0x20, Rev = 0x05, 100baseT, FDX
PHY 0x01: OUI = 0x0688, Model = 0x20, Rev = 0x05, 100baseT, FDX
read err 3
a2: read: EMAC_STACR=0xffffc043, i=4
read err 3
a2: read: EMAC_STACR=0xffffc063, i=4
read err 3
a2: read: EMAC_STACR=0xffffc083, i=4
read err 3
a2: read: EMAC_STACR=0xffffc0a3, i=4
read err 3

=> mii read 0 0
3000
=> mii read 0 1
786D
=> mii read 0 2
001A
=> mii read 0 3
2205
=> mii read 1 0
3000
=> mii read 1 1
786D
=> mii read 1 2
001A
=> mii read 1 3
2205
=> mii read 2 0
read err 3
a2: read: EMAC_STACR=0xffffc040, i=4
Error reading from the PHY
2205
=> mii read 2 1
read err 3
a2: read: EMAC_STACR=0xffffc041, i=4
Error reading from the PHY
2205
=> mii read 2 2
read err 3
a2: read: EMAC_STACR=0xffffc042, i=4
Error reading from the PHY
2205
=> mii read 2 3
read err 3
a2: read: EMAC_STACR=0xffffc043, i=4
Error reading from the PHY
2205

My previously posted patch to fix the "even-numbered" problem will not
work in this case!


Dave

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Re: 405 MII-PHY communication problem (was: Re: PPC405gp enet Soft Reset)

[Stefan Roese]

David,

just to let you know:

We have PPC405GP Rev D & Rev E running @ 198 MHz with Intel LXT971LE @
address 0, and seem to have none of your described problem:

=> mii info
PHY 0x00: OUI = 0x04DE, Model = 0x0E, Rev = 0x01, 100baseT, FDX
read err 3
a2: read: EMAC_STACR=0xffffc023, i=3
read err 3
a2: read: EMAC_STACR=0xffffc043, i=3
read err 3

etc...

Stefan Roese


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Re: 405 MII-PHY communication problem (was: Re: PPC405gp enet Soft Reset)

[David Müller (ELSOFT AG)]

Hi

The problem with the even-numbered PHY register addresses seems to be
caused by a too weak or totally missing pullup resistor on the MDIO line.

David Müller (ELSOFT AG) wrote:
>
> Hi
>
> andrew may wrote:
>
>> On Mon, Feb 11, 2002 at 12:55:05PM +0100, David Müller (ELSOFT AG) wrote:
>>
>>> Hi
>>>
>>> andrew may wrote:
>>>
>>>> Here is a log from ppcboot since it is easy to test this there
>>>> without doing
>>>> a kernel build. My phy is at address 0x1f.
>>>>
>>>> => mii read 0x1 2
>>>> 07FF
>>>> => mii read 0x1 3
>>>> read err 3
>>>> a2: read: EMAC_STACR=0xffffc023, i=2
>>>> Error reading from the PHY
>>>> 07FF
>>>>
>>>>
>>> I'm seeing this error too on our boards. But i'm not certain, if it's a
>>> problem of the MII controller in the 405 or a problem of the LXT971.
>>> What revision of the 405 do you have? What clock frequency your 405
>>> run at?
>>>

[old stuff deleted]



Dave

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Re: 405 MII-PHY communication problem (was: Re: PPC405gp enet Soft Reset)

[Stefan Roese]

We are using a 4k7 pullup, and seem to have no problems.

> -----Ursprüngliche Nachricht-----
> Von: David Müller (ELSOFT AG) [mailto:d.mueller@elsoft.ch]
> Gesendet: Dienstag, 19. Februar 2002 13:06
> An: David Müller (ELSOFT AG)
> Cc: andrew may; Armin; Stefan Roese;
> linuxppc-embedded@lists.linuxppc.org
> Betreff: Re: 405 MII-PHY communication problem (was: Re: PPC405gp enet
> Soft Reset)
>
>
> Hi
>
> The problem with the even-numbered PHY register addresses seems to be
> caused by a too weak or totally missing pullup resistor on the MDIO line.
>
> David Müller (ELSOFT AG) wrote:
> >
> > Hi
> >
> > andrew may wrote:
> >
> >> On Mon, Feb 11, 2002 at 12:55:05PM +0100, David Müller (ELSOFT
> AG) wrote:
> >>
> >>> Hi
> >>>
> >>> andrew may wrote:
> >>>
> >>>> Here is a log from ppcboot since it is easy to test this there
> >>>> without doing
> >>>> a kernel build. My phy is at address 0x1f.
> >>>>
> >>>> => mii read 0x1 2
> >>>> 07FF
> >>>> => mii read 0x1 3
> >>>> read err 3
> >>>> a2: read: EMAC_STACR=0xffffc023, i=2
> >>>> Error reading from the PHY
> >>>> 07FF
> >>>>
> >>>>
> >>> I'm seeing this error too on our boards. But i'm not certain,
> if it's a
> >>> problem of the MII controller in the 405 or a problem of the LXT971.
> >>> What revision of the 405 do you have? What clock frequency your 405
> >>> run at?
> >>>
>
> [old stuff deleted]
>
>
>
> Dave
>
>


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Re: 405 MII-PHY communication problem (was: Re: PPC405gp enet Soft Reset)

[andrew may]

On Tue, Feb 19, 2002 at 01:05:44PM +0100, David Müller (ELSOFT AG) wrote:
> Hi
>
> The problem with the even-numbered PHY register addresses seems to be
> caused by a too weak or totally missing pullup resistor on the MDIO line.

Yep, that seems to solve it here as, well. The phy wants a 1.5k pull up.

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