pci_consistent_alloc & mpc107 snoop

pci_consistent_alloc & mpc107 snoop

[Neil Wilson]

Hi,

I hope someone can enlighten me .....

Am I right in thinking that pci_consistent_alloc gets me
uncached memory ?, if not is there an easy way to modify the pages allocated
?

The reason being is that we have an mpc7450/mpc107 board with a custom
pci ethernet card (it runs a modified pcnet32 driver) and also a soft
ethernet
port in an fpga.  The hardware designer reckons we are getting stung with a
motorola 7450 errata (#46 if anyone is interested), where the 7450 can hang
during signalling retries with the 107.

Our hardware designer therefore wants the pci ethernet to use uncached
buffers &
also to have the 107 pci snoop disabled.  I have disabled snoop in the boot
code (ppcboot) and the ethernet card still works, but now it does not work
under Linux (it used to be fine with snoop enabled, nfs etc all worked).

Any ideas ....?

Thanks.

Neil


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Re: pci_consistent_alloc & mpc107 snoop

[Dan Malek]

Neil Wilson wrote:

> I hope someone can enlighten me .....

Heh :-)

> Am I right in thinking that pci_consistent_alloc gets me
> uncached memory ?, if not is there an easy way to modify the pages allocated
> ?

It's gets memory for you that is dma consistent, not necessarily uncached.
It will be uncached on processors that don't have cache snooping, but
it will be cached on processors that are known to snoop the bus.


> Our hardware designer therefore wants the pci ethernet to use uncached
> buffers &
> also to have the 107 pci snoop disabled.

Linux usually assumes major hardware features work :-)  There are working
boards with 7450/107 combinations.  I don't know what your fpga may be
doing that causes problems.

> ....  I have disabled snoop in the boot
> code (ppcboot) and the ethernet card still works, but now it does not work
> under Linux (it used to be fine with snoop enabled, nfs etc all worked).

You need to tell Linux the processor doesn't support snooping.  There is
a configuration option CONFIG_NOT_COHERENT_CACHE that we use on processors
that don't have cache snooping, but I don't know how well it will work
in your case.  I know the cache management functions are not designed to
work with L2 and L3 caches, so there will be lots of work needed to keep
the caches on a 74xx consistent.


> Any ideas ....?

I would certainly verify this "errata" is causing the trouble before making
the software changes necessary to support a non-snooping 74xx processor.
I'm not sure how much of an "errata" this is or simply the desire to eliminate
some backward compatibility to improve bus performance.  I would also find
a way to measure the performance impact of such a system design, as the
multiple level caches and bus snooping appear to be a significant part of
the system performance.  It seems weird to invest in the power of the 7450 and
then cripple it by not using these features.

Good luck.


	-- Dan


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