Re: MDIO clock speed computation

[Dan Malek <dan@embeddededge.com>]

Jean-Denis Boyer wrote:

> However, your fix seems incomplete.
> If I have a frequency of 82,5MHz, for example,
> it yields exactly to the same result before and after your patch,
> that is an MDIO clock of 2.58MHz.

The MII clock is not derived from the core speed, but rather the
system/bus clock speed.  Up to this point, I don't believe there are
any 8xx parts that are qualified to run beyond a 50 MHz CPU/bus
speed, so the software is just fine.  If you are running something
faster than a 50 MHz bus, you may want to look into this.


>
> Since the divisor is 2 * MDCLOCK,
> I would suggest something like:
>
>   (((bd->bi_intfreq + (2 * 2500000 - 1 )) / 2500000 / 2) & 0x3F) << 1;

The proper fix would be to change this from 'bi_intfreq' to 'bi_busfreq'.

What is actually happening is you are running much slower than 2.5 MHz
because you are computing on a clock that is running much faster than
the actual supplied clock to the MII (i.e. your divisor is too large).
Also, the 2.5 MHz is a suggestion, I think all PHYs run much faster, you
will have to check the data sheet.  The Motorola manual used to indicate
this as a suggested maximum for their parts, further that it would
run faster than this and maximum was still being qualified.

The only thing that will happen if this speed is out of spec for either
side is you will have problems configuring or detecting the PHY (the exchange
of control/status messages).  It has nothing to do with data transfer.


	-- Dan


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