From: Jan Damborsky <Jan.Damborsky@devcom.cz>
To: linuxppc-embedded@lists.linuxppc.org
Subject: Problem with data cache on MPC823E
Date: Tue, 21 Jan 2003 17:28:12 +0100 [thread overview]
Message-ID: <3E2D751C.7000001@devcom.cz> (raw)
Hello people,
we have developed our board with MPC823E, FLASH memory
DRAM memory for embedded Linux porting, but we have problem
with data cache. From time to time when CPU wants load data from DRAM
to data cache, it makes four burst-reads instead of one for loading one
cache line.
After this, all four words in cache line are loaded with the same first
"critical word".
We don't know, why CPU repeats this burst-read four times. May be it is
because we have floating BI (burst inhibit) CPU singnal.
We have set BIH bit in UPMA to zero.
When setting this BIH bit to one (burst inhibit), all works well.
Does anybody have any help ?
Jan Damborsky
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next reply other threads:[~2003-01-21 16:28 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-01-21 16:28 Jan Damborsky [this message]
2003-01-21 19:49 ` Problem with data cache on MPC823E Wolfgang Denk
2003-01-22 9:05 ` Jan Damborsky
-- strict thread matches above, loose matches on Subject: below --
2003-01-21 20:40 Wells, Charles
2003-01-22 9:02 ` Jan Damborsky
[not found] <DF2B720CF774D21189EE00805FA7FA220517835A@nmrusdunsx3.nielsenmedia.com>
2003-01-27 7:42 ` Jan Damborsky
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