From: Dan Malek <dan@embeddededge.com>
To: Roland Dreier <roland@topspin.com>
Cc: Joakim Tjernlund <Joakim.Tjernlund@lumentis.se>,
Linuxppc-Embedded <linuxppc-embedded@lists.linuxppc.org>
Subject: Re: question on howto use invalidate_dcache_range
Date: Thu, 13 Mar 2003 13:39:50 -0500 [thread overview]
Message-ID: <3E70D076.7030507@embeddededge.com> (raw)
In-Reply-To: 52k7f3t9ic.fsf@topspin.com
Roland Dreier wrote:
> Is the following not possible:
That's a problem in any system design. Consider what would happen
if you had an architecture that was hardware cache coherent.
Software that writes to buffers at any time that is also a
DMA target will result in unpredictable behavior. The system
design for what you described requires a higher level of
shared memory software synchronization as it is exactly the
unpredictability that has to be prevented in any SMP design.
What you described is a real problem with cache unaligned
buffers that has to be avoided in systems that do not have
hardware cache coherency.
-- Dan
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2003-03-13 18:39 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-03-12 11:20 question on howto use invalidate_dcache_range Stephan Linke
2003-03-13 7:40 ` Joakim Tjernlund
2003-03-13 11:00 ` Stephan Linke
2003-03-13 13:24 ` Joakim Tjernlund
2003-03-13 15:04 ` Stephan Linke
2003-03-13 16:27 ` Dan Malek
2003-03-13 17:54 ` Joakim Tjernlund
2003-03-13 18:06 ` Dan Malek
2003-03-13 18:19 ` Roland Dreier
2003-03-13 18:39 ` Dan Malek [this message]
2003-03-13 19:09 ` Roland Dreier
2003-03-13 21:54 ` Joakim Tjernlund
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