RE: Disabling data cache

RE: Disabling data cache

[Jean-Denis Boyer]

There is a kernel configuration option for that: CONFIG_DCACHE_DISABLE.
In the kernel configuration UI, look into the section 'MPC8260 CPM Options'.

Regards,
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Re: Disabling data cache

[Matt Porter]

On Wed, Apr 02, 2003 at 09:28:21AM -0500, Jean-Denis Boyer wrote:
>
> There is a kernel configuration option for that: CONFIG_DCACHE_DISABLE.
> In the kernel configuration UI, look into the section 'MPC8260 CPM Options'.

There is no code backing that option in linuxppc_2_4_devel, it is useless.
Certainly one could take what one person did (in the old post I referenced)
and put it under a config option for debug purposes.  Yet another nice
project for somebody. :)

Regards,
--
Matt Porter
porter@cox.net
This is Linux Country. On a quiet night, you can hear Windows reboot.

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Re: Disabling data cache

[Dan Malek]

Matt Porter wrote:

> On Wed, Apr 02, 2003 at 09:28:21AM -0500, Jean-Denis Boyer wrote:
>
>>There is a kernel configuration option for that: CONFIG_DCACHE_DISABLE.
>>In the kernel configuration UI, look into the section 'MPC8260 CPM Options'.
>
>
> There is no code backing that option in linuxppc_2_4_devel, it is useless.

It was orginally done for 8xx processors.  I suspect someone (I don't
think it was me) :-) tried to consolidate 8xx and 82xx CPM configurations
and messed it up.

> Certainly one could take what one person did (in the old post I referenced)
> and put it under a config option for debug purposes.  Yet another nice
> project for somebody. :)

Data cache configuration options are a PITA for most processors.  You would
have to litter #ifdefs all over the kernel.  IMHO, you should make cache
coherent busses work correctly, then write code.  In the case of 8xx, it is
a trival bit setting in one control register that can be done at start up
time, making debug easier for this non-coherent cache processor.

This #ifdef used to be near the end of initial_mmu() in head_8xx.S.  When
I added the TLB Pinning option, I decided to simplify the code and remove
the disable data cache option.  If necessary, it is easy to do this with
a simple code change.  The copyback #ifdef is a little more useful as we
are more likely to see memory controller set up rather than data cache
coherency problems these days and this option can help debug those.

I'll remove the configuration option.

Thanks.


	-- Dan


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Re: Disabling data cache

[Tom Rini]

On Wed, Apr 02, 2003 at 02:23:01PM -0500, Dan Malek wrote:
>
> Matt Porter wrote:
>
> >On Wed, Apr 02, 2003 at 09:28:21AM -0500, Jean-Denis Boyer wrote:
> >
> >>There is a kernel configuration option for that: CONFIG_DCACHE_DISABLE.
> >>In the kernel configuration UI, look into the section 'MPC8260 CPM
> >>Options'.
> >
> >
> >There is no code backing that option in linuxppc_2_4_devel, it is useless.
>
> It was orginally done for 8xx processors.  I suspect someone (I don't
> think it was me) :-) tried to consolidate 8xx and 82xx CPM configurations
> and messed it up.

My guess and recollection is that the 8260 version of this was to
disable the DCACHE in a certain manner, because of buggy silicon on a
specific board.  Someone unmerged this bit of code later I think.

--
Tom Rini
http://gate.crashing.org/~trini/

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Re: Disabling data cache

[Wolfgang Denk]

In message <20030402194622.GA30107@ip68-0-152-218.tc.ph.cox.net> you wrote:
>
> > It was orginally done for 8xx processors.  I suspect someone (I don't
> > think it was me) :-) tried to consolidate 8xx and 82xx CPM configurations
> > and messed it up.
>
> My guess and recollection is that the 8260 version of this was to
> disable the DCACHE in a certain manner, because of buggy silicon on a
> specific board.  Someone unmerged this bit of code later I think.

It might have been me. We had problems on  the  first  prototypes  of
TQM8260 boards; the board configuration with L2 cache would only work
with  DC turned off. The problem disappeared with later silicon, so I
never checked again what happened with the code.

Wolfgang Denk

--
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@denx.de
Intel told us the Pentium would have "RISK" features...

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Re: Disabling data cache

[Tom Rini]

On Wed, Apr 02, 2003 at 10:19:09PM +0200, Wolfgang Denk wrote:
>
> In message <20030402194622.GA30107@ip68-0-152-218.tc.ph.cox.net> you wrote:
> >
> > > It was orginally done for 8xx processors.  I suspect someone (I don't
> > > think it was me) :-) tried to consolidate 8xx and 82xx CPM configurations
> > > and messed it up.
> >
> > My guess and recollection is that the 8260 version of this was to
> > disable the DCACHE in a certain manner, because of buggy silicon on a
> > specific board.  Someone unmerged this bit of code later I think.
>
> It might have been me. We had problems on  the  first  prototypes  of
> TQM8260 boards; the board configuration with L2 cache would only work
> with  DC turned off. The problem disappeared with later silicon, so I
> never checked again what happened with the code.

So the question now is do you still care about this case, or can it go
away in the public tree?

--
Tom Rini
http://gate.crashing.org/~trini/

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Re: Disabling data cache

[Wolfgang Denk]

In message <20030403145906.GA3867@ip68-0-152-218.tc.ph.cox.net> you wrote:
>
> > It might have been me. We had problems on  the  first  prototypes  of
> > TQM8260 boards; the board configuration with L2 cache would only work
> > with  DC turned off. The problem disappeared with later silicon, so I
> > never checked again what happened with the code.
>
> So the question now is do you still care about this case, or can it go
> away in the public tree?

I don't care. Nobody buys such old hardware any more.

Best regards,

Wolfgang Denk

--
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@denx.de
Every little picofarad has a nanohenry all its own.      - Don Vonada

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Re: Disabling data cache

[Dan Malek]

Tom Rini wrote:

> My guess and recollection is that the 8260 version of this was to
> disable the DCACHE in a certain manner, because of buggy silicon on a
> specific board.  Someone unmerged this bit of code later I think.

Hmm....OK.  FYI, on any processor core except 8xx you can't disable
the data cache and expect to make any progress without also removing
the cache management instructions.  That would be a pretty ugly patch
and also require unique libraries for the applications. :-)


	-- Dan


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Re: Disabling data cache

[Ralph Blach]

Yes, I gave it a breif test and it did not work and I did not have time to
debug it.

Chip


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Disabling data cache

[kas turi]

Hi
  We have a custom made board and we are running 8250
processor. We are using DMA to transmit and receive
data between peripheral and memory. The data is
getting corrupted while transmitting and receiving. We
are suspecting it might be due to data cache being
enabled. So I disabled data cache in the routine
enable_cache in the file arch/ppc/kernel/head.S. I
rebuilt the kernel and when I run on my board it hangs
after printing "Now booting the kernel". I would like
to know why the kernel is not booting up. I have
enclosed the console output:

Transfering control to linux (at address 00400040)
loaded at : 00400040   0040b340
relocated to : 00400000 0040b300
board data at: 007FFE40 007FFEF8
relocated to: 0040B148  0040B200
image at:     0040B340  004B6026
avail ram:    004B7000  04000000

Linux/PPC load: console=ttyS0,9600
root=/dev/mtdblock/1
Uncompressing linux
Now booting the kernel

Also I would like to understand what is the use of ESE
bit in SIUMCR. Should this bit be always enabled
whenever data cache is enabled.

Any help is appreciated.

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http://platinum.yahoo.com

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Re: Disabling data cache

[Matt Porter]

On Tue, Apr 01, 2003 at 05:34:34PM -0800, kas turi wrote:
>
> Hi
>   We have a custom made board and we are running 8250
> processor. We are using DMA to transmit and receive
> data between peripheral and memory. The data is
> getting corrupted while transmitting and receiving. We
> are suspecting it might be due to data cache being
> enabled. So I disabled data cache in the routine
> enable_cache in the file arch/ppc/kernel/head.S. I
> rebuilt the kernel and when I run on my board it hangs
> after printing "Now booting the kernel". I would like
> to know why the kernel is not booting up. I have
> enclosed the console output:

Sure, you are hitting a number of places in early init
where the kernel uses dcbz.  You need to "fix" those areas
and hack the BAT setting to cache inhibit the DBATs that
map lowmem.  If you search the list archives, I recall an
old email describing what somebody did in detail to run
with dcache disabled on a classic PPC core.

Regards,
--
Matt Porter
porter@cox.net
This is Linux Country. On a quiet night, you can hear Windows reboot.

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