From: "Mark A. Greer" <mgreer@mvista.com>
To: ghannon@cspi.com
Cc: ??? <ksshin@essetel.com>, linuxppc-embedded@lists.linuxppc.org
Subject: Re: interrupt handling in 7410+64260
Date: Wed, 27 Aug 2003 10:22:07 -0700 [thread overview]
Message-ID: <3F4CE8BF.1090003@mvista.com> (raw)
In-Reply-To: <85256D8F.004ABAE9.00@pine.cspi.com>
ghannon@cspi.com wrote:
>>2. request_irq(77, ...)
>> 77 means bit 15 of GPP_INTERRUPT_CAUSE register.
>>
>>
>
>There is an offset of 64, try 79 vs 77 to get bit 15.
>
>
Yep, 79 sounds right, if its GPP 15.
Mark
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2003-08-27 17:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-08-27 13:38 interrupt handling in 7410+64260 ghannon
2003-08-27 17:22 ` Mark A. Greer [this message]
-- strict thread matches above, loose matches on Subject: below --
2003-08-27 2:21 신경수
2003-08-27 3:18 ` Paul White
2003-08-27 4:23 ` ???
2003-08-27 17:21 ` Mark A. Greer
2003-09-08 4:49 ` ???
2003-09-08 5:38 ` Dan Kegel
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