Re: 405 TLB miss reduction

[Dan Malek <dan@embeddededge.com>]

Wolfgang Grandegger wrote:

> Increasing the page size from 4 to 8 kB should, in theory, halve the
> page misses (if no large TLB pages are used).

It depends entirely on locality of reference.  Without doing any
kind execution analysis (which isn't the proper engineering practice)
you could assume it would help instruction pages and have little effect
on data pages.

> ... Unfortunately, increasing
> the page size seem not straight forward as it's statically used in
> various places and maybe the GLIBC needs to be rebuild as well.

The MIPS port uses various (but static) page sizes depending upon
the requirements of the processor core.  IIRC, their glibc can handle
this at run time.  Maybe Drow can add some comments here.  In any case
there are already kernel and user reference ports we should leverage
if we intend to go down this path.


Thanks.


	-- Dan


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