* [PATCH] Restore PERR/SERR bit settings during EEH device recovery
@ 2008-07-08 3:18 Mike Mason
2008-07-08 13:38 ` Linas Vepstas
0 siblings, 1 reply; 4+ messages in thread
From: Mike Mason @ 2008-07-08 3:18 UTC (permalink / raw)
To: paulus, benh, linasvepstas, linuxppc-dev
The following patch restores the PERR and SERR bits in the PCI
command register during an EEH device recovery.
We have found at least one case (an Agilent test card) where the
PERR/SERR bits are set to 1 by firmware at boot time, but are
not restored to 1 during EEH recovery. The patch fixes the
Agilent card problem. It has been tested on several other
EEH-enabled cards with no regressions.
Signed-off-by: Mike Mason <mmlnx@us.ibm.com>
--- linux-2.6.26-rc9/arch/powerpc/platforms/pseries/eeh.c 2008-07-07 16:06:57.000000000 -0700
+++ linux-2.6.26-rc9-new/arch/powerpc/platforms/pseries/eeh.c 2008-07-07 16:11:10.000000000 -0700
@@ -812,6 +812,7 @@
static inline void __restore_bars (struct pci_dn *pdn)
{
int i;
+ u32 cmd;
if (NULL==pdn->phb) return;
for (i=4; i<10; i++) {
@@ -832,6 +833,15 @@
/* max latency, min grant, interrupt pin and line */
rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
+
+ /* Restore PERR & SERR bits, some devices require it,
+ don't touch the other command bits */
+ rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
+ if (pdn->config_space[1] & PCI_COMMAND_PARITY)
+ cmd |= PCI_COMMAND_PARITY;
+ if (pdn->config_space[1] & PCI_COMMAND_SERR)
+ cmd |= PCI_COMMAND_SERR;
+ rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
}
/**
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] Restore PERR/SERR bit settings during EEH device recovery
2008-07-08 3:18 [PATCH] Restore PERR/SERR bit settings during EEH device recovery Mike Mason
@ 2008-07-08 13:38 ` Linas Vepstas
2008-07-08 15:56 ` Mike Mason
2008-07-08 16:04 ` Mike Mason
0 siblings, 2 replies; 4+ messages in thread
From: Linas Vepstas @ 2008-07-08 13:38 UTC (permalink / raw)
To: Mike Mason; +Cc: paulus, linuxppc-dev
2008/7/7 Mike Mason <mmlnx@us.ibm.com>:
> The following patch restores the PERR and SERR bits in the PCI
> command register during an EEH device recovery.
> We have found at least one case (an Agilent test card) where the
> PERR/SERR bits are set to 1 by firmware at boot time, but are
> not restored to 1 during EEH recovery.
Any chance they should be zero, and were accidentally set to 1?
In which case, you'd need an else clause, below.
> The patch fixes the
> Agilent card problem. It has been tested on several other EEH-enabled cards
> with no regressions.
>
> Signed-off-by: Mike Mason <mmlnx@us.ibm.com>
>
> --- linux-2.6.26-rc9/arch/powerpc/platforms/pseries/eeh.c 2008-07-07
> 16:06:57.000000000 -0700
> +++ linux-2.6.26-rc9-new/arch/powerpc/platforms/pseries/eeh.c 2008-07-07
> 16:11:10.000000000 -0700
> @@ -812,6 +812,7 @@
> static inline void __restore_bars (struct pci_dn *pdn)
> {
> int i;
> + u32 cmd;
>
> if (NULL==pdn->phb) return;
> for (i=4; i<10; i++) {
> @@ -832,6 +833,15 @@
>
> /* max latency, min grant, interrupt pin and line */
> rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
> +
> + /* Restore PERR & SERR bits, some devices require it,
> + don't touch the other command bits */
> + rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
> + if (pdn->config_space[1] & PCI_COMMAND_PARITY)
> + cmd |= PCI_COMMAND_PARITY;
else cmd &= ~PCI_COMMAND_PARITY;
> + if (pdn->config_space[1] & PCI_COMMAND_SERR)
> + cmd |= PCI_COMMAND_SERR;
else cmd &= ~PCI_COMMAND_SERR;
> + rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
> }
Other than that, I'll add an
Acked-by: Linas Vepstas <linasvepstas@gmail.com>
--linas
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] Restore PERR/SERR bit settings during EEH device recovery
2008-07-08 13:38 ` Linas Vepstas
@ 2008-07-08 15:56 ` Mike Mason
2008-07-08 16:04 ` Mike Mason
1 sibling, 0 replies; 4+ messages in thread
From: Mike Mason @ 2008-07-08 15:56 UTC (permalink / raw)
To: linasvepstas; +Cc: paulus, linuxppc-dev
Linas Vepstas wrote:
> 2008/7/7 Mike Mason <mmlnx@us.ibm.com>:
>> The following patch restores the PERR and SERR bits in the PCI
>> command register during an EEH device recovery.
>> We have found at least one case (an Agilent test card) where the
>> PERR/SERR bits are set to 1 by firmware at boot time, but are
>> not restored to 1 during EEH recovery.
>
> Any chance they should be zero, and were accidentally set to 1?
> In which case, you'd need an else clause, below.
I suppose it's possible. I'll add your suggestion and resubmit.
Mike
>
>> The patch fixes the
>> Agilent card problem. It has been tested on several other EEH-enabled cards
>> with no regressions.
>>
>> Signed-off-by: Mike Mason <mmlnx@us.ibm.com>
>>
>> --- linux-2.6.26-rc9/arch/powerpc/platforms/pseries/eeh.c 2008-07-07
>> 16:06:57.000000000 -0700
>> +++ linux-2.6.26-rc9-new/arch/powerpc/platforms/pseries/eeh.c 2008-07-07
>> 16:11:10.000000000 -0700
>> @@ -812,6 +812,7 @@
>> static inline void __restore_bars (struct pci_dn *pdn)
>> {
>> int i;
>> + u32 cmd;
>>
>> if (NULL==pdn->phb) return;
>> for (i=4; i<10; i++) {
>> @@ -832,6 +833,15 @@
>>
>> /* max latency, min grant, interrupt pin and line */
>> rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
>> +
>> + /* Restore PERR & SERR bits, some devices require it,
>> + don't touch the other command bits */
>> + rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
>> + if (pdn->config_space[1] & PCI_COMMAND_PARITY)
>> + cmd |= PCI_COMMAND_PARITY;
>
> else cmd &= ~PCI_COMMAND_PARITY;
>
>> + if (pdn->config_space[1] & PCI_COMMAND_SERR)
>> + cmd |= PCI_COMMAND_SERR;
>
> else cmd &= ~PCI_COMMAND_SERR;
>
>> + rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
>> }
>
> Other than that, I'll add an
>
> Acked-by: Linas Vepstas <linasvepstas@gmail.com>
>
> --linas
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] Restore PERR/SERR bit settings during EEH device recovery
2008-07-08 13:38 ` Linas Vepstas
2008-07-08 15:56 ` Mike Mason
@ 2008-07-08 16:04 ` Mike Mason
1 sibling, 0 replies; 4+ messages in thread
From: Mike Mason @ 2008-07-08 16:04 UTC (permalink / raw)
To: linasvepstas, paulus, benh, linuxppc-dev
Here's a resubmission of the patch with Linas' suggestion.
The following patch restores the PERR and SERR bits in the PCI
command register during an EEH device recovery. We have found
at least one case (an Agilent test card) where the PERR/SERR
bits are set to 1 by firmware at boot time, but are not restored
to 1 during EEH recovery. The patch fixes the Agilent card
problem. It has been tested on several other EEH-enabled cards
with no regressions.
Signed-off-by: Mike Mason <mmlnx@us.ibm.com>
Acked-by: Linas Vepstas <linasvepstas@gmail.com>
--- linux-2.6.26-rc9/arch/powerpc/platforms/pseries/eeh.c 2008-07-07 16:06:57.000000000 -0700
+++ linux-2.6.26-rc9-new/arch/powerpc/platforms/pseries/eeh.c 2008-07-08 03:56:35.000000000 -0700
@@ -812,6 +812,7 @@
static inline void __restore_bars (struct pci_dn *pdn)
{
int i;
+ u32 cmd;
if (NULL==pdn->phb) return;
for (i=4; i<10; i++) {
@@ -832,6 +833,19 @@
/* max latency, min grant, interrupt pin and line */
rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
+
+ /* Restore PERR & SERR bits, some devices require it,
+ don't touch the other command bits */
+ rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
+ if (pdn->config_space[1] & PCI_COMMAND_PARITY)
+ cmd |= PCI_COMMAND_PARITY;
+ else
+ cmd &= ~PCI_COMMAND_PARITY;
+ if (pdn->config_space[1] & PCI_COMMAND_SERR)
+ cmd |= PCI_COMMAND_SERR;
+ else
+ cmd &= ~PCI_COMMAND_SERR;
+ rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
}
/**
^ permalink raw reply [flat|nested] 4+ messages in thread
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2008-07-08 3:18 [PATCH] Restore PERR/SERR bit settings during EEH device recovery Mike Mason
2008-07-08 13:38 ` Linas Vepstas
2008-07-08 15:56 ` Mike Mason
2008-07-08 16:04 ` Mike Mason
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