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Date: Sat, 1 Aug 2009 17:55:58 -0500
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Subject: Re: [PATCH 3/3] Support for PCI Express reset type
From: Linas Vepstas <linasvepstas@gmail.com>
To: Mike Mason <mmlnx@us.ibm.com>
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Cc: linuxppc-dev@ozlabs.org, Richard Lary <rlary@us.ibm.com>,
	Paul Mackerras <paulus@samba.org>, linux-pci@vger.kernel.org
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2009/7/30 Mike Mason <mmlnx@us.ibm.com>:
> This is the third of three patches that implement a bit field that PCI
> Express device drivers can use to indicate they need a fundamental reset
> during error recovery.
>
> By default, the EEH framework on powerpc does what's known as a "hot rese=
t"
> during recovery of a PCI Express device. =C2=A0We've found a case where t=
he
> device needs a "fundamental reset" to recover properly. =C2=A0The current=
 PCI
> error recovery and EEH frameworks do not support this distinction.
>
> The attached patch makes changes to EEH to utilize the new bit field.
>
> These patches supersede the previously submitted patch that implemented a
> fundamental reset bit field.
>
> Please review and let me know of any concerns.
>
> Signed-off-by: Mike Mason <mmlnx@us.ibm.com>
> Signed-off-by: Richard Lary <rlary@us.ibm.com>

Signed-off-by: Linas Vepstas <linasvepstas@gmail.com>

> + =C2=A0 =C2=A0 =C2=A0 /* Determine type of EEH reset required by device,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0* default hot reset or fundamental reset
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
> + =C2=A0 =C2=A0 =C2=A0 if (dev->needs_freset)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rtas_pci_slot_reset(pd=
n, 3);
> + =C2=A0 =C2=A0 =C2=A0 else
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rtas_pci_slot_reset(pd=
n, 1);

Gack!  I remember deluges of emails and conference calls
where the hardware guys went on about this; and I admit I didn't
quite get it, which I guess is why this patch is showing up many
years late.

FWIW some of the variants of the IPR chipset almost surely
need the freset  bit set.

--linas