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To: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>,
 benh@kernel.crashing.org, paulus@samba.org
From: Michael Ellerman <mpe@ellerman.id.au>
Cc: linuxppc-dev@lists.ozlabs.org,
 "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: Re: [V2, 02/10] powerpc/mm/radix: Update to tlb functions ric argument
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Date: Wed, 15 Jun 2016 22:37:03 +1000 (AEST)
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On Wed, 2016-08-06 at 14:25:50 UTC, "Aneesh Kumar K.V" wrote:
> Radix invalidate control (RIC) is used to control which cache to flush
> using tlb instructions. When doing a PID flush, we currently flush
> everything including page walk cache. For address range flush, we flush
> only the TLB. In the later patch, we add support for flushing only
> page walk cache.
> 
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>

Applied to powerpc fixes, thanks.

https://git.kernel.org/powerpc/c/36194812a4063dd2a72070aec3

cheers