From: Michael Ellerman <mpe@ellerman.id.au>
To: Ian Munsie <imunsie@au1.ibm.com>,
Michael Neuling <mikey@neuling.org>,
Frederic Barrat <fbarrat@linux.vnet.ibm.com>,
Andrew Donnellan <andrew.donnellan@au1.ibm.com>,
linuxppc-dev@lists.ozlabs.org, Huy Nguyen <huyn@mellanox.com>
Cc: Ian Munsie <imunsie@au1.ibm.com>
Subject: Re: [11/15] cxl: Add support for interrupts on the Mellanox CX4
Date: Fri, 15 Jul 2016 20:53:25 +1000 (AEST) [thread overview]
Message-ID: <3rrTv935SZz9snm@ozlabs.org> (raw)
In-Reply-To: <1468444634-1866-12-git-send-email-imunsie@au.ibm.com>
On Wed, 2016-13-07 at 21:17:10 UTC, Ian Munsie wrote:
> From: Ian Munsie <imunsie@au1.ibm.com>
>
> The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where
> interrupts are routed from the networking hardware to the XSL using the
> MSIX table, and from there will be transformed back into an MSIX
> interrupt using the cxl style interrupts (i.e. using IVTE entries and
> ranges to map a PE and AFU interrupt number to an MSIX address).
>
> We want to hide the implementation details of cxl interrupts as much as
> possible. To this end, we use a special version of the MSI setup &
> teardown routines in the PHB while in cxl mode to allocate the cxl
> interrupts and configure the IVTE entries in the process element.
>
> This function does not configure the MSIX table - the CX4 card uses a
> custom format in that table and it would not be appropriate to fill that
> out in generic code. The rest of the functionality is similar to the
> "Full MSI-X mode" described in the CAIA, and this could be easily
> extended to support other adapters that use that mode in the future.
>
> The interrupts will be associated with the default context. If the
> maximum number of interrupts per context has been limited (e.g. by the
> mlx5 driver), it will automatically allocate additional kernel contexts
> to associate extra interrupts as required. These contexts will be
> started using the same WED that was used to start the default context.
>
> Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/a2f67d5ee8d950caaa7a6144cf
cheers
next prev parent reply other threads:[~2016-07-15 10:53 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-13 21:16 [PATCH v3] powerpc / cxl: Add support for the Mellanox CX4 in cxl mode Ian Munsie
2016-07-13 21:17 ` [PATCH 01/15] powerpc/powernv: Split cxl code out into a separate file Ian Munsie
2016-07-15 10:53 ` [01/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 02/15] cxl: Add cxl_slot_is_supported API Ian Munsie
2016-07-15 10:53 ` [02/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 03/15] cxl: Enable bus mastering for devices using CAPP DMA mode Ian Munsie
2016-07-15 10:53 ` [03/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 04/15] cxl: Move cxl_afu_get / cxl_afu_put to base Ian Munsie
2016-07-15 10:53 ` [04/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 05/15] cxl: Allow a default context to be associated with an external pci_dev Ian Munsie
2016-07-15 10:53 ` [05/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 06/15] cxl: Do not create vPHB if there are no AFU configuration records Ian Munsie
2016-07-15 10:53 ` [06/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 07/15] powerpc/powernv: Add support for the cxl kernel api on the real phb Ian Munsie
2016-07-15 10:53 ` [07/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 08/15] cxl: Add support for using the kernel API with a real PHB Ian Munsie
2016-07-15 10:53 ` [08/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 09/15] cxl: Add kernel APIs to get & set the max irqs per context Ian Munsie
2016-07-15 10:53 ` [09/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 10/15] cxl: Add preliminary workaround for CX4 interrupt limitation Ian Munsie
2016-07-15 10:53 ` [10/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 11/15] cxl: Add support for interrupts on the Mellanox CX4 Ian Munsie
2016-07-14 5:34 ` Andrew Donnellan
2016-07-15 10:53 ` Michael Ellerman [this message]
2016-07-13 21:17 ` [PATCH 12/15] cxl: Workaround PE=0 hardware limitation in " Ian Munsie
2016-07-15 10:53 ` [12/15] " Michael Ellerman
2016-07-28 1:48 ` [PATCH 12/15] " Andrew Donnellan
2016-07-13 21:17 ` [PATCH 13/15] PCI/hotplug: pnv_php: export symbols and move struct types needed by cxl Ian Munsie
2016-07-15 10:53 ` [13/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 14/15] PCI/hotplug: pnv_php: handle OPAL_PCI_SLOT_OFFLINE power state Ian Munsie
2016-07-15 10:53 ` [14/15] " Michael Ellerman
2016-07-13 21:17 ` [PATCH 15/15] cxl: Add cxl_check_and_switch_mode() API to switch bi-modal cards Ian Munsie
2016-07-15 10:53 ` [15/15] " Michael Ellerman
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