* [PATCH v3 1/2] powernv: Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h @ 2016-08-05 12:04 Mahesh J Salgaonkar 2016-08-05 12:04 ` [PATCH v3 2/2] powernv: Fix MCE handler to avoid trashing CR0/CR1 registers Mahesh J Salgaonkar 2016-08-09 11:26 ` [v3,1/2] powernv: Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h Michael Ellerman 0 siblings, 2 replies; 5+ messages in thread From: Mahesh J Salgaonkar @ 2016-08-05 12:04 UTC (permalink / raw) To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman Cc: Stewart Smith, Vaidyanathan Srinivasan From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h so that MCE handler changes in subsequent patch can use it. No functionality change. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> --- Change in v3: - Rebase to Linus' master. --- arch/powerpc/include/asm/cpuidle.h | 13 +++++++++++++ arch/powerpc/kernel/idle_book3s.S | 12 ------------ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h index 3d7fc06..01b8a13 100644 --- a/arch/powerpc/include/asm/cpuidle.h +++ b/arch/powerpc/include/asm/cpuidle.h @@ -19,4 +19,17 @@ extern u64 pnv_first_deep_stop_state; #endif +/* Idle state entry routines */ +#ifdef CONFIG_PPC_P7_NAP +#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \ + /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \ + std r0,0(r1); \ + ptesync; \ + ld r0,0(r1); \ +1: cmp cr0,r0,r0; \ + bne 1b; \ + IDLE_INST; \ + b . +#endif /* CONFIG_PPC_P7_NAP */ + #endif diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S index 8a56a51..7a41f13 100644 --- a/arch/powerpc/kernel/idle_book3s.S +++ b/arch/powerpc/kernel/idle_book3s.S @@ -44,18 +44,6 @@ PSSCR_PSLL_MASK | PSSCR_TR_MASK | \ PSSCR_MTL_MASK -/* Idle state entry routines */ - -#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \ - /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \ - std r0,0(r1); \ - ptesync; \ - ld r0,0(r1); \ -1: cmp cr0,r0,r0; \ - bne 1b; \ - IDLE_INST; \ - b . - .text /* ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 2/2] powernv: Fix MCE handler to avoid trashing CR0/CR1 registers. 2016-08-05 12:04 [PATCH v3 1/2] powernv: Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h Mahesh J Salgaonkar @ 2016-08-05 12:04 ` Mahesh J Salgaonkar 2016-08-05 22:39 ` Benjamin Herrenschmidt 2016-08-09 11:26 ` [v3, " Michael Ellerman 2016-08-09 11:26 ` [v3,1/2] powernv: Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h Michael Ellerman 1 sibling, 2 replies; 5+ messages in thread From: Mahesh J Salgaonkar @ 2016-08-05 12:04 UTC (permalink / raw) To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman Cc: Stewart Smith, Shreyas B. Prabhu, Vaidyanathan Srinivasan From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> The current implementation of MCE early handling modifies CR0/1 registers without saving its old values. Fix this by moving early check for powersaving mode to machine_check_handle_early(). The power architecture 2.06 or later allows the possibility of getting machine check while in nap/sleep/winkle. The last bit of HSPRG0 is set to 1, if thread is woken up from winkle. Hence, clear the last bit of HSPRG0 (r13) before MCE handler starts using it as paca pointer. Also, the current code always puts the thread into nap state irrespective of whatever idle state it woke up from. Fix that by looking at paca->thread_idle_state and put the thread back into same state where it came from. Reported-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Reviewed-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> --- Change in v3: - Rebase to Linus' master. Change in v2: - Call IDLE_STATE_ENTER_SEQ(PPC_NAP) instead of power7_enter_nap_mode() to be consistent with other part of code. --- arch/powerpc/kernel/exceptions-64s.S | 69 ++++++++++++++++++++-------------- 1 file changed, 40 insertions(+), 29 deletions(-) diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 694def6..a59c9cc 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -144,29 +144,14 @@ machine_check_pSeries_1: * vector */ SET_SCRATCH0(r13) /* save r13 */ -#ifdef CONFIG_PPC_P7_NAP -BEGIN_FTR_SECTION - /* Running native on arch 2.06 or later, check if we are - * waking up from nap. We only handle no state loss and - * supervisor state loss. We do -not- handle hypervisor - * state loss at this time. + /* + * Running native on arch 2.06 or later, we may wakeup from winkle + * inside machine check. If yes, then last bit of HSPGR0 would be set + * to 1. Hence clear it unconditionally. */ - mfspr r13,SPRN_SRR1 - rlwinm. r13,r13,47-31,30,31 - OPT_GET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR) - beq 9f - - mfspr r13,SPRN_SRR1 - rlwinm. r13,r13,47-31,30,31 - /* waking up from powersave (nap) state */ - cmpwi cr1,r13,2 - /* Total loss of HV state is fatal. let's just stay stuck here */ - OPT_GET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR) - bgt cr1,. -9: - OPT_SET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR) -END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) -#endif /* CONFIG_PPC_P7_NAP */ + GET_PACA(r13) + clrrdi r13,r13,1 + SET_PACA(r13) EXCEPTION_PROLOG_0(PACA_EXMC) BEGIN_FTR_SECTION b machine_check_powernv_early @@ -1273,25 +1258,51 @@ machine_check_handle_early: * Check if thread was in power saving mode. We come here when any * of the following is true: * a. thread wasn't in power saving mode - * b. thread was in power saving mode with no state loss or - * supervisor state loss + * b. thread was in power saving mode with no state loss, + * supervisor state loss or hypervisor state loss. * - * Go back to nap again if (b) is true. + * Go back to nap/sleep/winkle mode again if (b) is true. */ rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ beq 4f /* No, it wasn;t */ /* Thread was in power saving mode. Go back to nap again. */ cmpwi r11,2 - bne 3f - /* Supervisor state loss */ + blt 3f + /* Supervisor/Hypervisor state loss */ li r0,1 stb r0,PACA_NAPSTATELOST(r13) 3: bl machine_check_queue_event MACHINE_CHECK_HANDLER_WINDUP GET_PACA(r13) ld r1,PACAR1(r13) - li r3,PNV_THREAD_NAP - b pnv_enter_arch207_idle_mode + /* + * Check what idle state this CPU was in and go back to same mode + * again. + */ + lbz r3,PACA_THREAD_IDLE_STATE(r13) + cmpwi r3,PNV_THREAD_NAP + bgt 10f + IDLE_STATE_ENTER_SEQ(PPC_NAP) + /* No return */ +10: + cmpwi r3,PNV_THREAD_SLEEP + bgt 2f + IDLE_STATE_ENTER_SEQ(PPC_SLEEP) + /* No return */ + +2: + /* + * Go back to winkle. Please note that this thread was woken up in + * machine check from winkle and have not restored the per-subcore + * state. Hence before going back to winkle, set last bit of HSPGR0 + * to 1. This will make sure that if this thread gets woken up + * again at reset vector 0x100 then it will get chance to restore + * the subcore state. + */ + ori r13,r13,1 + SET_PACA(r13) + IDLE_STATE_ENTER_SEQ(PPC_WINKLE) + /* No return */ 4: #endif /* ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 2/2] powernv: Fix MCE handler to avoid trashing CR0/CR1 registers. 2016-08-05 12:04 ` [PATCH v3 2/2] powernv: Fix MCE handler to avoid trashing CR0/CR1 registers Mahesh J Salgaonkar @ 2016-08-05 22:39 ` Benjamin Herrenschmidt 2016-08-09 11:26 ` [v3, " Michael Ellerman 1 sibling, 0 replies; 5+ messages in thread From: Benjamin Herrenschmidt @ 2016-08-05 22:39 UTC (permalink / raw) To: Mahesh J Salgaonkar, linuxppc-dev, Paul Mackerras, Michael Ellerman Cc: Stewart Smith, Shreyas B. Prabhu, Vaidyanathan Srinivasan On Fri, 2016-08-05 at 17:34 +0530, Mahesh J Salgaonkar wrote: > From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> > > The current implementation of MCE early handling modifies CR0/1 > registers > without saving its old values. Fix this by moving early check for > powersaving mode to machine_check_handle_early(). CC stable ? > The power architecture 2.06 or later allows the possibility of > getting > machine check while in nap/sleep/winkle. The last bit of HSPRG0 is > set > to 1, if thread is woken up from winkle. Hence, clear the last bit of > HSPRG0 (r13) before MCE handler starts using it as paca pointer. > > Also, the current code always puts the thread into nap state > irrespective > of whatever idle state it woke up from. Fix that by looking at > paca->thread_idle_state and put the thread back into same state where > it > came from. > > Reported-by: Paul Mackerras <paulus@samba.org> > Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> > Reviewed-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> > --- > Change in v3: > - Rebase to Linus' master. > > Change in v2: > - Call IDLE_STATE_ENTER_SEQ(PPC_NAP) instead of > power7_enter_nap_mode() > to be consistent with other part of code. > --- > arch/powerpc/kernel/exceptions-64s.S | 69 ++++++++++++++++++++-- > ------------ > 1 file changed, 40 insertions(+), 29 deletions(-) > > diff --git a/arch/powerpc/kernel/exceptions-64s.S > b/arch/powerpc/kernel/exceptions-64s.S > index 694def6..a59c9cc 100644 > --- a/arch/powerpc/kernel/exceptions-64s.S > +++ b/arch/powerpc/kernel/exceptions-64s.S > @@ -144,29 +144,14 @@ machine_check_pSeries_1: > * vector > */ > SET_SCRATCH0(r13) /* save r13 */ > -#ifdef CONFIG_PPC_P7_NAP > -BEGIN_FTR_SECTION > - /* Running native on arch 2.06 or later, check if we are > - * waking up from nap. We only handle no state loss and > - * supervisor state loss. We do -not- handle hypervisor > - * state loss at this time. > + /* > + * Running native on arch 2.06 or later, we may wakeup from > winkle > + * inside machine check. If yes, then last bit of HSPGR0 > would be set > + * to 1. Hence clear it unconditionally. > */ > - mfspr r13,SPRN_SRR1 > - rlwinm. r13,r13,47-31,30,31 > - OPT_GET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR) > - beq 9f > - > - mfspr r13,SPRN_SRR1 > - rlwinm. r13,r13,47-31,30,31 > - /* waking up from powersave (nap) state */ > - cmpwi cr1,r13,2 > - /* Total loss of HV state is fatal. let's just stay stuck > here */ > - OPT_GET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR) > - bgt cr1,. > -9: > - OPT_SET_SPR(r13, SPRN_CFAR, CPU_FTR_CFAR) > -END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) > -#endif /* CONFIG_PPC_P7_NAP */ > + GET_PACA(r13) > + clrrdi r13,r13,1 > + SET_PACA(r13) > EXCEPTION_PROLOG_0(PACA_EXMC) > BEGIN_FTR_SECTION > b machine_check_powernv_early > @@ -1273,25 +1258,51 @@ machine_check_handle_early: > * Check if thread was in power saving mode. We come here > when any > * of the following is true: > * a. thread wasn't in power saving mode > - * b. thread was in power saving mode with no state loss or > - * supervisor state loss > + * b. thread was in power saving mode with no state loss, > + * supervisor state loss or hypervisor state loss. > * > - * Go back to nap again if (b) is true. > + * Go back to nap/sleep/winkle mode again if (b) is true. > */ > rlwinm. r11,r12,47-31,30,31 /* Was it in power > saving mode? */ > beq 4f /* No, it wasn;t */ > /* Thread was in power saving mode. Go back to nap again. */ > cmpwi r11,2 > - bne 3f > - /* Supervisor state loss */ > + blt 3f > + /* Supervisor/Hypervisor state loss */ > li r0,1 > stb r0,PACA_NAPSTATELOST(r13) > 3: bl machine_check_queue_event > MACHINE_CHECK_HANDLER_WINDUP > GET_PACA(r13) > ld r1,PACAR1(r13) > - li r3,PNV_THREAD_NAP > - b pnv_enter_arch207_idle_mode > + /* > + * Check what idle state this CPU was in and go back to same > mode > + * again. > + */ > + lbz r3,PACA_THREAD_IDLE_STATE(r13) > + cmpwi r3,PNV_THREAD_NAP > + bgt 10f > + IDLE_STATE_ENTER_SEQ(PPC_NAP) > + /* No return */ > +10: > + cmpwi r3,PNV_THREAD_SLEEP > + bgt 2f > + IDLE_STATE_ENTER_SEQ(PPC_SLEEP) > + /* No return */ > + > +2: > + /* > + * Go back to winkle. Please note that this thread was woken > up in > + * machine check from winkle and have not restored the per- > subcore > + * state. Hence before going back to winkle, set last bit of > HSPGR0 > + * to 1. This will make sure that if this thread gets woken > up > + * again at reset vector 0x100 then it will get chance to > restore > + * the subcore state. > + */ > + ori r13,r13,1 > + SET_PACA(r13) > + IDLE_STATE_ENTER_SEQ(PPC_WINKLE) > + /* No return */ > 4: > #endif > /* ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [v3, 2/2] powernv: Fix MCE handler to avoid trashing CR0/CR1 registers. 2016-08-05 12:04 ` [PATCH v3 2/2] powernv: Fix MCE handler to avoid trashing CR0/CR1 registers Mahesh J Salgaonkar 2016-08-05 22:39 ` Benjamin Herrenschmidt @ 2016-08-09 11:26 ` Michael Ellerman 1 sibling, 0 replies; 5+ messages in thread From: Michael Ellerman @ 2016-08-09 11:26 UTC (permalink / raw) To: Mahesh Salgaonkar, linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras Cc: Stewart Smith, Shreyas B. Prabhu On Fri, 2016-05-08 at 12:04:13 UTC, Mahesh Salgaonkar wrote: > From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> > > The current implementation of MCE early handling modifies CR0/1 registers > without saving its old values. Fix this by moving early check for > powersaving mode to machine_check_handle_early(). > > The power architecture 2.06 or later allows the possibility of getting > machine check while in nap/sleep/winkle. The last bit of HSPRG0 is set > to 1, if thread is woken up from winkle. Hence, clear the last bit of > HSPRG0 (r13) before MCE handler starts using it as paca pointer. > > Also, the current code always puts the thread into nap state irrespective > of whatever idle state it woke up from. Fix that by looking at > paca->thread_idle_state and put the thread back into same state where it > came from. > > Reported-by: Paul Mackerras <paulus@samba.org> > Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> > Reviewed-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Applied to powerpc fixes, thanks. https://git.kernel.org/powerpc/c/bc14c49195e49b3231c01e4c44 cheers ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [v3,1/2] powernv: Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h 2016-08-05 12:04 [PATCH v3 1/2] powernv: Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h Mahesh J Salgaonkar 2016-08-05 12:04 ` [PATCH v3 2/2] powernv: Fix MCE handler to avoid trashing CR0/CR1 registers Mahesh J Salgaonkar @ 2016-08-09 11:26 ` Michael Ellerman 1 sibling, 0 replies; 5+ messages in thread From: Michael Ellerman @ 2016-08-09 11:26 UTC (permalink / raw) To: Mahesh Salgaonkar, linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras Cc: Stewart Smith On Fri, 2016-05-08 at 12:04:04 UTC, Mahesh Salgaonkar wrote: > From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> > > Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h so that MCE handler changes > in subsequent patch can use it. > > No functionality change. > > Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Applied to powerpc fixes, thanks. https://git.kernel.org/powerpc/c/98d8821a47f3fd7354d3ab87ad cheers ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-08-09 11:26 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-08-05 12:04 [PATCH v3 1/2] powernv: Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h Mahesh J Salgaonkar 2016-08-05 12:04 ` [PATCH v3 2/2] powernv: Fix MCE handler to avoid trashing CR0/CR1 registers Mahesh J Salgaonkar 2016-08-05 22:39 ` Benjamin Herrenschmidt 2016-08-09 11:26 ` [v3, " Michael Ellerman 2016-08-09 11:26 ` [v3,1/2] powernv: Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h Michael Ellerman
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