From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vClL31JrlzDq5s for ; Wed, 1 Feb 2017 12:05:31 +1100 (AEDT) In-Reply-To: <1485333389-5752-2-git-send-email-ego@linux.vnet.ibm.com> To: "Gautham R. Shenoy" , Benjamin Herrenschmidt , Paul Mackerras , "Rafael J. Wysocki" , Daniel Lezcano , Michael Neuling , Vaidyanathan Srinivasan , "Shreyas B. Prabhu" , Shilpasri G Bhat , Stewart Smith , Balbir Singh , "Oliver O'Halloran" , Rob Herring From: Michael Ellerman Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, "Gautham R. Shenoy" , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [v6,1/5] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro Message-Id: <3vClL26Q2hz9rxw@ozlabs.org> Date: Wed, 1 Feb 2017 12:05:30 +1100 (AEDT) List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Wed, 2017-01-25 at 08:36:25 UTC, "Gautham R. Shenoy" wrote: > From: "Gautham R. Shenoy" > > Currently all the low-power idle states are expected to wake up > at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ > that puts the CPU to an idle state and never returns. > > On ISA v3.0, when the ESL and EC bits in the PSSCR are zero, the CPU > is expected to wake up at the next instruction of the idle > instruction. > > This patch adds a new macro named IDLE_STATE_ENTER_SEQ_NORET for the > no-return variant and reuses the name IDLE_STATE_ENTER_SEQ > for a variant that allows resuming operation at the instruction next > to the idle-instruction. > > Acked-by: Balbir Singh > Signed-off-by: Gautham R. Shenoy Series applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/823b7bd5156a93872d9561b3f033df cheers