From: Michael Ellerman <patch-notifications@ellerman.id.au>
To: Alexey Kardashevskiy <aik@ozlabs.ru>, linuxppc-dev@lists.ozlabs.org
Cc: Alexey Kardashevskiy <aik@ozlabs.ru>,
David Gibson <david@gibson.dropbear.id.au>,
Gavin Shan <gwshan@linux.vnet.ibm.com>
Subject: Re: [kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested
Date: Tue, 14 Mar 2017 22:45:54 +1100 (AEDT) [thread overview]
Message-ID: <3vjCc35p6Qz9s5g@ozlabs.org> (raw)
In-Reply-To: <20170222044359.3663-1-aik@ozlabs.ru>
On Wed, 2017-02-22 at 04:43:59 UTC, Alexey Kardashevskiy wrote:
> The IODA2 specification says that a 64 DMA address cannot use top 4 bits
> (3 are reserved and one is a "TVE select"); bottom page_shift bits
> cannot be used for multilevel table addressing either.
>
> The existing IODA2 table allocation code aligns the minimum TCE table
> size to PAGE_SIZE so in the case of 64K system pages and 4K IOMMU pages,
> we have 64-4-12=48 bits. Since 64K page stores 8192 TCEs, i.e. needs
> 13 bits, the maximum number of levels is 48/13 = 3 so we physically
> cannot address more and EEH happens on DMA accesses.
>
> This adds a check that too many levels were requested.
>
> It is still possible to have 5 levels in the case of 4K system page size.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Applied to powerpc fixes, thanks.
https://git.kernel.org/powerpc/c/7aafac11e308d37ed3c509829bb43d
cheers
prev parent reply other threads:[~2017-03-14 11:45 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-22 4:43 [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested Alexey Kardashevskiy
2017-02-27 0:53 ` Gavin Shan
2017-02-27 11:00 ` Michael Ellerman
2017-02-28 0:54 ` Alexey Kardashevskiy
2017-03-05 23:03 ` Benjamin Herrenschmidt
2017-03-06 1:28 ` Alexey Kardashevskiy
2017-03-06 3:36 ` Benjamin Herrenschmidt
2017-03-06 4:02 ` Alexey Kardashevskiy
2017-03-14 11:45 ` Michael Ellerman [this message]
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