From: Michael Ellerman <patch-notifications@ellerman.id.au>
To: Michael Ellerman <mpe@ellerman.id.au>, linuxppc-dev@ozlabs.org
Cc: aneesh.kumar@linux.vnet.ibm.com, anton@samba.org
Subject: Re: [v2,1/2] powerpc/mm/radix: Optimise Page Walk Cache flush
Date: Thu, 27 Apr 2017 20:30:57 +1000 (AEST) [thread overview]
Message-ID: <3wDCsF6P2Sz9sNZ@ozlabs.org> (raw)
In-Reply-To: <1493213240-5260-1-git-send-email-mpe@ellerman.id.au>
On Wed, 2017-04-26 at 13:27:19 UTC, Michael Ellerman wrote:
> Currently we implement flushing of the page walk cache (PWC) by calling
> _tlbiel_pid() with a RIC (Radix Invalidation Control) value of 1 which says to
> only flush the PWC.
>
> But _tlbiel_pid() loops over each set (congruence class) of the TLB, which is
> not necessary when we're just flushing the PWC.
>
> In fact the set argument is ignored for a PWC flush, so essentially we're just
> flushing the PWC 127 extra times for no benefit.
>
> Fix it by adding tlbiel_pwc() which just does a single flush of the PWC.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> [mpe: Split out of combined patch, drop _ in name, rewrite change log]
> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Series applied to powerpc next.
https://git.kernel.org/powerpc/c/5a9853946c2e7a5ef9ef5302ecada6
cheers
prev parent reply other threads:[~2017-04-27 10:30 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-26 13:27 [PATCH v2 1/2] powerpc/mm/radix: Optimise Page Walk Cache flush Michael Ellerman
2017-04-26 13:27 ` [PATCH v2 2/2] powerpc/mm/radix: Optimise tlbiel flush all case Michael Ellerman
2017-04-27 10:30 ` Michael Ellerman [this message]
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