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From: Michael Ellerman <patch-notifications@ellerman.id.au>
To: Nicholas Piggin <npiggin@gmail.com>, linuxppc-dev@lists.ozlabs.org
Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>,
	Nicholas Piggin <npiggin@gmail.com>
Subject: Re: [v2, 3/3] powerpc/64s/radix: Fix process table entry cache invalidation
Date: Wed,  8 Nov 2017 10:30:19 +1100 (AEDT)	[thread overview]
Message-ID: <3yWlyz3fDyz9t2Z@ozlabs.org> (raw)
In-Reply-To: <20171024130654.1223-4-npiggin@gmail.com>

On Tue, 2017-10-24 at 13:06:54 UTC, Nicholas Piggin wrote:
> According to the architecture, the process table entry cache must be
> flushed with tlbie RIC=2.
> 
> Currently the process table entry is set to invalid right before the
> PID is returned to the allocator, with no invalidation. This works on
> existing implementations that are known to not cache the process table
> entry for any except the current PIDR.
> 
> It is architecturally correct and cleaner to invalidate with RIC=2
> after clearing the process table entry and before the PID is returned
> to the allocator. This can be done in arch_exit_mmap that runs before
> the final flush, and to ensure the final flush (fullmm) is always a
> RIC=2 variant.
> 
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/30b49ec798f0984b905fd94d1957d6

cheers

      parent reply	other threads:[~2017-11-07 23:30 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-24 13:06 [PATCH v2 0/3] powerpc/64s/radix: misc minor TLB flush fixes Nicholas Piggin
2017-10-24 13:06 ` [PATCH v2 1/3] powerpc/64s/radix: fix preempt imbalance in TLB flush Nicholas Piggin
2017-10-26  6:52   ` Aneesh Kumar K.V
2017-11-01  5:17   ` [v2,1/3] " Michael Ellerman
2017-10-24 13:06 ` [PATCH v2 2/3] powerpc/64s/radix: tlbie improve preempt handling Nicholas Piggin
2017-10-26  6:53   ` Aneesh Kumar K.V
2017-11-07 23:30   ` [v2,2/3] " Michael Ellerman
2017-10-24 13:06 ` [PATCH v2 3/3] powerpc/64s/radix: Fix process table entry cache invalidation Nicholas Piggin
2017-10-26  6:53   ` Aneesh Kumar K.V
2017-11-07 23:30   ` Michael Ellerman [this message]

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