From: Michael Ellerman <patch-notifications@ellerman.id.au>
To: Paul Mackerras <paulus@ozlabs.org>,
kvm@vger.kernel.org, linuxppc-dev@ozlabs.org
Cc: kvm-ppc@vger.kernel.org
Subject: Re: [4/6] KVM: PPC: Book3S HV: Improve handling of debug-trigger HMIs on POWER9
Date: Mon, 22 Jan 2018 14:34:28 +1100 (AEDT) [thread overview]
Message-ID: <3zPxr63rD9z9sCZ@ozlabs.org> (raw)
In-Reply-To: <1516182675-25331-5-git-send-email-paulus@ozlabs.org>
On Wed, 2018-01-17 at 09:51:13 UTC, Paul Mackerras wrote:
> Hypervisor maintenance interrupts (HMIs) are generated by various
> causes, signalled by bits in the hypervisor maintenance exception
> register (HMER). In most cases calling OPAL to handle the interrupt
> is the correct thing to do, but the "debug trigger" HMIs signalled by
> PPC bit 17 (bit 46) of HMER are used to invoke software workarounds
> for hardware bugs, and OPAL does not have any code to handle this
> cause. The debug trigger HMI is used in POWER9 DD2.0 and DD2.1 chips
> to work around a hardware bug in executing vector load instructions to
> cache inhibited memory. In POWER9 DD2.2 chips, it is generated when
> conditions are detected relating to threads being in TM (transactional
> memory) suspended mode when the core SMT configuration needs to be
> reconfigured.
>
> The kernel currently has code to detect the vector CI load condition,
> but only when the HMI occurs in the host, not when it occurs in a
> guest. If a HMI occurs in the guest, it is always passed to OPAL, and
> then we always re-sync the timebase, because the HMI cause might have
> been a timebase error, for which OPAL would re-sync the timebase, thus
> removing the timebase offset which KVM applied for the guest. Since
> we don't know what OPAL did, we don't know whether to subtract the
> timebase offset from the timebase, so instead we re-sync the timebase.
>
> This adds code to determine explicitly what the cause of a debug
> trigger HMI will be. This is based on a new device-tree property
> under the CPU nodes called ibm,hmi-special-triggers, if it is
> present, or otherwise based on the PVR (processor version register).
> The handling of debug trigger HMIs is pulled out into a separate
> function which can be called from the KVM guest exit code. If this
> function handles and clears the HMI, and no other HMI causes remain,
> then we skip calling OPAL and we proceed to subtract the guest
> timebase offset from the timebase.
>
> The overall handling for HMIs that occur in the host (i.e. not in a
> KVM guest) is largely unchanged, except that we now don't set the flag
> for the vector CI load workaround on DD2.2 processors.
>
> This also removes a BUG_ON in the KVM code. BUG_ON is generally not
> useful in KVM guest entry/exit code since it is difficult to handle
> the resulting trap gracefully.
>
> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/d075745d893c78730e4a3b7a60fca2
cheers
next prev parent reply other threads:[~2018-01-22 3:34 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-17 9:51 [PATCH 0/6] KVM: PPC: Book3S HV: Changes for POWER9 v2.2 support Paul Mackerras
2018-01-17 9:51 ` [PATCH 1/6] KVM: PPC: Book3S HV: Make sure we don't re-enter guest without XIVE loaded Paul Mackerras
2018-01-17 9:51 ` [PATCH 2/6] KVM: PPC: Book3S HV: Do SLB load/unload with guest LPCR value loaded Paul Mackerras
2018-01-17 9:51 ` [PATCH 3/6] KVM: PPC: Book3S HV: Allow HPT and radix on the same core for POWER9 v2.2 Paul Mackerras
2018-01-17 11:14 ` Benjamin Herrenschmidt
2018-01-18 1:27 ` Paul Mackerras
2018-01-18 1:51 ` Benjamin Herrenschmidt
2018-01-17 9:51 ` [PATCH 4/6] KVM: PPC: Book3S HV: Improve handling of debug-trigger HMIs on POWER9 Paul Mackerras
2018-01-22 3:34 ` Michael Ellerman [this message]
2018-01-17 9:51 ` [PATCH 5/6] powerpc: Add a CPU feature bit for TM bug workarounds on POWER9 v2.2 Paul Mackerras
2018-01-17 9:51 ` [PATCH 6/6] KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9 Paul Mackerras
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