* [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in
@ 2013-03-13 19:07 Kumar Gala
2013-03-13 19:07 ` [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale Kumar Gala
` (3 more replies)
0 siblings, 4 replies; 15+ messages in thread
From: Kumar Gala @ 2013-03-13 19:07 UTC (permalink / raw)
To: linuxppc-dev
Move to keeping the SoC registers that control and config the PCI
controllers on FSL SoCs in the pci_controller struct. This allows us to
not need to ioremap() the registers in multiple different places that
use them.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/include/asm/pci-bridge.h | 5 ++-
arch/powerpc/sysdev/fsl_pci.c | 69 ++++++++++++++-------------------
2 files changed, 34 insertions(+), 40 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 025a130..c0278f0 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -70,6 +70,8 @@ struct pci_controller {
* BIG_ENDIAN - cfg_addr is a big endian register
* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
* the PLB4. Effectively disable MRM commands by setting this.
+ * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
+ * link status is in a RC PCIe cfg register (vs being a SoC register)
*/
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
@@ -77,6 +79,7 @@ struct pci_controller {
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
+#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
u32 indirect_type;
/* Currently, we limit ourselves to 1 IO range and 3 mem
* ranges since the common pci_bus structure can't handle more
@@ -90,9 +93,9 @@ struct pci_controller {
#ifdef CONFIG_PPC64
unsigned long buid;
+#endif /* CONFIG_PPC64 */
void *private_data;
-#endif /* CONFIG_PPC64 */
};
/* These are used for config access before all the PCI probing
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 3271177..41bbcc4 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -54,34 +54,22 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
return;
}
-static int __init fsl_pcie_check_link(struct pci_controller *hose,
- struct resource *rsrc)
+static int __init fsl_pcie_check_link(struct pci_controller *hose)
{
- struct ccsr_pci __iomem *pci = NULL;
u32 val;
- /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
- if (rsrc) {
- pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
- (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
- pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
- if (!pci) {
- dev_err(hose->parent, "Unable to map PCIe registers\n");
- return -ENOMEM;
- }
- if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_3_0) {
- val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
- >> PEX_CSR0_LTSSM_SHIFT;
- if (val != PEX_CSR0_LTSSM_L0)
- return 1;
- iounmap(pci);
- return 0;
- }
- iounmap(pci);
+ if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
+ early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
+ if (val < PCIE_LTSSM_L0)
+ return 1;
+ } else {
+ struct ccsr_pci __iomem *pci = hose->private_data;
+ /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
+ val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
+ >> PEX_CSR0_LTSSM_SHIFT;
+ if (val != PEX_CSR0_LTSSM_L0)
+ return 1;
}
- early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
- if (val < PCIE_LTSSM_L0)
- return 1;
return 0;
}
@@ -148,10 +136,9 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
}
/* atmu setup for fsl pci/pcie controller */
-static void setup_pci_atmu(struct pci_controller *hose,
- struct resource *rsrc)
+static void setup_pci_atmu(struct pci_controller *hose)
{
- struct ccsr_pci __iomem *pci;
+ struct ccsr_pci __iomem *pci = hose->private_data;
int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
u64 mem, sz, paddr_hi = 0;
u64 paddr_lo = ULLONG_MAX;
@@ -162,15 +149,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
const u64 *reg;
int len;
- pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
- (u64)rsrc->start, (u64)resource_size(rsrc));
-
- pci = ioremap(rsrc->start, resource_size(rsrc));
- if (!pci) {
- dev_err(hose->parent, "Unable to map ATMU registers\n");
- return;
- }
-
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
win_idx = 2;
@@ -451,6 +429,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
const int *bus_range;
u8 hdr_type, progif;
struct device_node *dev;
+ struct ccsr_pci __iomem *pci;
dev = pdev->dev.of_node;
@@ -483,9 +462,19 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
hose->first_busno = bus_range ? bus_range[0] : 0x0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
+ pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
+ (u64)rsrc.start, (u64)resource_size(&rsrc));
+
+ pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
+ if (!hose->private_data)
+ goto no_bridge;
+
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
PPC_INDIRECT_TYPE_BIG_ENDIAN);
+ if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
+ hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
+
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
/* For PCIE read HEADER_TYPE to identify controler mode */
early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
@@ -505,7 +494,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
- if (fsl_pcie_check_link(hose, &rsrc))
+ if (fsl_pcie_check_link(hose))
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
}
@@ -522,11 +511,12 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
pci_process_bridge_OF_ranges(hose, dev, is_primary);
/* Setup PEX window registers */
- setup_pci_atmu(hose, &rsrc);
+ setup_pci_atmu(hose);
return 0;
no_bridge:
+ iounmap(hose->private_data);
/* unmap cfg_data & cfg_addr separately if not on same page */
if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
((unsigned long)hose->cfg_addr & PAGE_MASK))
@@ -703,11 +693,12 @@ static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
WARN_ON(hose->dn->data);
hose->dn->data = pcie;
hose->ops = &mpc83xx_pcie_ops;
+ hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
- if (fsl_pcie_check_link(hose, NULL))
+ if (fsl_pcie_check_link(hose))
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
return 0;
--
1.7.9.7
^ permalink raw reply related [flat|nested] 15+ messages in thread* [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale 2013-03-13 19:07 [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in Kumar Gala @ 2013-03-13 19:07 ` Kumar Gala 2013-03-14 9:43 ` Rojhalat Ibrahim 2013-04-08 8:20 ` [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in Rojhalat Ibrahim ` (2 subsequent siblings) 3 siblings, 1 reply; 15+ messages in thread From: Kumar Gala @ 2013-03-13 19:07 UTC (permalink / raw) To: linuxppc-dev; +Cc: Rojhalat Ibrahim From: Rojhalat Ibrahim <imr@rtschenk.de> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/include/asm/pci-bridge.h | 6 ++++++ arch/powerpc/sysdev/fsl_pci.c | 37 +++++++++++++++++++++++++++++---- arch/powerpc/sysdev/indirect_pci.c | 10 ++++----- 3 files changed, 43 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h index c0278f0..ffbc5fd 100644 --- a/arch/powerpc/include/asm/pci-bridge.h +++ b/arch/powerpc/include/asm/pci-bridge.h @@ -120,6 +120,12 @@ extern void setup_indirect_pci(struct pci_controller* hose, resource_size_t cfg_addr, resource_size_t cfg_data, u32 flags); +extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val); + +extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 val); + static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) { return bus->sysdata; diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 41bbcc4..b18c377 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -74,6 +74,35 @@ static int __init fsl_pcie_check_link(struct pci_controller *hose) return 0; } +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) +{ + struct pci_controller *hose = pci_bus_to_host(bus); + + /* check the link status */ + if ((bus->number == hose->first_busno) && (devfn == 0)) { + if (fsl_pcie_check_link(hose)) + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; + else + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; + } + return indirect_read_config(bus, devfn, offset, len, val); +} + +static struct pci_ops fsl_indirect_pci_ops = +{ + .read = fsl_indirect_read_config, + .write = indirect_write_config, +}; + +static void __init fsl_setup_indirect_pci(struct pci_controller* hose, + resource_size_t cfg_addr, + resource_size_t cfg_data, u32 flags) +{ + setup_indirect_pci(hose, cfg_addr, cfg_data, flags); + hose->ops = &fsl_indirect_pci_ops; +} + #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) #define MAX_PHYS_ADDR_BITS 40 @@ -469,8 +498,8 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) if (!hose->private_data) goto no_bridge; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, - PPC_INDIRECT_TYPE_BIG_ENDIAN); + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, + PPC_INDIRECT_TYPE_BIG_ENDIAN); if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; @@ -779,8 +808,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev) if (ret) goto err0; } else { - setup_indirect_pci(hose, rsrc_cfg.start, - rsrc_cfg.start + 4, 0); + fsl_setup_indirect_pci(hose, rsrc_cfg.start, + rsrc_cfg.start + 4, 0); } printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index 82fdad8..c6c8b52 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c @@ -20,9 +20,8 @@ #include <asm/pci-bridge.h> #include <asm/machdep.h> -static int -indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 *val) +int indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) { struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; @@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, return PCIBIOS_SUCCESSFUL; } -static int -indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 val) +int indirect_write_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 val) { struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; -- 1.7.9.7 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale 2013-03-13 19:07 ` [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale Kumar Gala @ 2013-03-14 9:43 ` Rojhalat Ibrahim 2013-03-14 20:35 ` Kumar Gala 0 siblings, 1 reply; 15+ messages in thread From: Rojhalat Ibrahim @ 2013-03-14 9:43 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On Wednesday 13 March 2013 14:07:16 Kumar Gala wrote: > diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c > index 41bbcc4..b18c377 100644 > --- a/arch/powerpc/sysdev/fsl_pci.c > +++ b/arch/powerpc/sysdev/fsl_pci.c > @@ -74,6 +74,35 @@ static int __init fsl_pcie_check_link(struct > pci_controller *hose) return 0; > } > > +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int > devfn, + int offset, int len, u32 *val) > +{ > + struct pci_controller *hose = pci_bus_to_host(bus); > + > + /* check the link status */ > + if ((bus->number == hose->first_busno) && (devfn == 0)) { > + if (fsl_pcie_check_link(hose)) > + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; > + else > + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; > + } > + return indirect_read_config(bus, devfn, offset, len, val); > +} > + This does not work because fsl_indirect_read_config calls fsl_pcie_check_link which calls early_read_config_dword which eventually calls fsl_indirect_read_config, so the kernel hangs in a recursion loop. Below is a modified patch that does work. Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de> --- arch/powerpc/include/asm/pci-bridge.h | 6 ++++ arch/powerpc/sysdev/fsl_pci.c | 51 ++++++++++++++++++++++++++++++---- arch/powerpc/sysdev/indirect_pci.c | 10 ++---- 3 files changed, 55 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h index c0278f0..ffbc5fd 100644 --- a/arch/powerpc/include/asm/pci-bridge.h +++ b/arch/powerpc/include/asm/pci-bridge.h @@ -120,6 +120,12 @@ extern void setup_indirect_pci(struct pci_controller* hose, resource_size_t cfg_addr, resource_size_t cfg_data, u32 flags); +extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val); + +extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 val); + static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) { return bus->sysdata; diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 41bbcc4..63740f6 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -54,12 +54,22 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev) return; } -static int __init fsl_pcie_check_link(struct pci_controller *hose) +static int fsl_indirect_read_config(struct pci_bus *, unsigned int, + int, int, u32 *); + +static int fsl_pcie_check_link(struct pci_controller *hose) { u32 val; if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { - early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); + if (hose->ops->read == fsl_indirect_read_config) { + struct pci_bus bus; + bus.number = 0; + bus.sysdata = hose; + bus.ops = hose->ops; + indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val); + } else + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); if (val < PCIE_LTSSM_L0) return 1; } else { @@ -74,6 +84,35 @@ static int __init fsl_pcie_check_link(struct pci_controller *hose) return 0; } +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) +{ + struct pci_controller *hose = pci_bus_to_host(bus); + + /* check the link status */ + if ((bus->number == hose->first_busno) && (devfn == 0)) { + if (fsl_pcie_check_link(hose)) + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; + else + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; + } + return indirect_read_config(bus, devfn, offset, len, val); +} + +static struct pci_ops fsl_indirect_pci_ops = +{ + .read = fsl_indirect_read_config, + .write = indirect_write_config, +}; + +static void __init fsl_setup_indirect_pci(struct pci_controller* hose, + resource_size_t cfg_addr, + resource_size_t cfg_data, u32 flags) +{ + setup_indirect_pci(hose, cfg_addr, cfg_data, flags); + hose->ops = &fsl_indirect_pci_ops; +} + #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) #define MAX_PHYS_ADDR_BITS 40 @@ -469,8 +508,8 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) if (!hose->private_data) goto no_bridge; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, - PPC_INDIRECT_TYPE_BIG_ENDIAN); + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, + PPC_INDIRECT_TYPE_BIG_ENDIAN); if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; @@ -779,8 +818,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev) if (ret) goto err0; } else { - setup_indirect_pci(hose, rsrc_cfg.start, - rsrc_cfg.start + 4, 0); + fsl_setup_indirect_pci(hose, rsrc_cfg.start, + rsrc_cfg.start + 4, 0); } printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index 82fdad8..c6c8b52 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c @@ -20,9 +20,8 @@ #include <asm/pci-bridge.h> #include <asm/machdep.h> -static int -indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 *val) +int indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) { struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; @@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, return PCIBIOS_SUCCESSFUL; } -static int -indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 val) +int indirect_write_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 val) { struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale 2013-03-14 9:43 ` Rojhalat Ibrahim @ 2013-03-14 20:35 ` Kumar Gala 2013-03-18 9:22 ` Rojhalat Ibrahim 0 siblings, 1 reply; 15+ messages in thread From: Kumar Gala @ 2013-03-14 20:35 UTC (permalink / raw) To: Rojhalat Ibrahim; +Cc: linuxppc-dev On Mar 14, 2013, at 4:43 AM, Rojhalat Ibrahim wrote: > On Wednesday 13 March 2013 14:07:16 Kumar Gala wrote: >> diff --git a/arch/powerpc/sysdev/fsl_pci.c = b/arch/powerpc/sysdev/fsl_pci.c >> index 41bbcc4..b18c377 100644 >> --- a/arch/powerpc/sysdev/fsl_pci.c >> +++ b/arch/powerpc/sysdev/fsl_pci.c >> @@ -74,6 +74,35 @@ static int __init fsl_pcie_check_link(struct >> pci_controller *hose) return 0; >> } >>=20 >> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned = int >> devfn, + int offset, int len, u32 = *val) >> +{ >> + struct pci_controller *hose =3D pci_bus_to_host(bus); >> + >> + /* check the link status */ >> + if ((bus->number =3D=3D hose->first_busno) && (devfn =3D=3D 0)) = { >> + if (fsl_pcie_check_link(hose)) >> + hose->indirect_type |=3D = PPC_INDIRECT_TYPE_NO_PCIE_LINK; >> + else >> + hose->indirect_type &=3D = ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; >> + } >> + return indirect_read_config(bus, devfn, offset, len, val); >> +} >> + >=20 > This does not work because fsl_indirect_read_config calls = fsl_pcie_check_link which calls early_read_config_dword which eventually = calls fsl_indirect_read_config, so the kernel hangs in a recursion loop. = Below is a modified patch that does work. ok, that makes sense, but I guess now its making me question the = following statement: > if ((bus->number =3D=3D hose->first_busno) && (devfn =3D=3D 0)) { Why do we have this conditional? - k= ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale 2013-03-14 20:35 ` Kumar Gala @ 2013-03-18 9:22 ` Rojhalat Ibrahim 2013-04-03 7:09 ` Rojhalat Ibrahim 0 siblings, 1 reply; 15+ messages in thread From: Rojhalat Ibrahim @ 2013-03-18 9:22 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On Thursday 14 March 2013 15:35:40 Kumar Gala wrote: > On Mar 14, 2013, at 4:43 AM, Rojhalat Ibrahim wrote: > > On Wednesday 13 March 2013 14:07:16 Kumar Gala wrote: > >> diff --git a/arch/powerpc/sysdev/fsl_pci.c > >> b/arch/powerpc/sysdev/fsl_pci.c > >> index 41bbcc4..b18c377 100644 > >> --- a/arch/powerpc/sysdev/fsl_pci.c > >> +++ b/arch/powerpc/sysdev/fsl_pci.c > >> @@ -74,6 +74,35 @@ static int __init fsl_pcie_check_link(struct > >> pci_controller *hose) return 0; > >> } > >> > >> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int > >> devfn, + int offset, int len, u32 *val) > >> +{ > >> + struct pci_controller *hose = pci_bus_to_host(bus); > >> + > >> + /* check the link status */ > >> + if ((bus->number == hose->first_busno) && (devfn == 0)) { > >> + if (fsl_pcie_check_link(hose)) > >> + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; > >> + else > >> + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; > >> + } > >> + return indirect_read_config(bus, devfn, offset, len, val); > >> +} > >> + > > > > This does not work because fsl_indirect_read_config calls > > fsl_pcie_check_link which calls early_read_config_dword which eventually > > calls fsl_indirect_read_config, so the kernel hangs in a recursion loop. > > Below is a modified patch that does work. > ok, that makes sense, but I guess now its making me question the following statement: > > if ((bus->number == hose->first_busno) && (devfn == 0)) { > > Why do we have this conditional? > > - k Right. This is not necessary anymore. I modified the patch accordingly. Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de> --- arch/powerpc/include/asm/pci-bridge.h | 6 ++++ arch/powerpc/sysdev/fsl_pci.c | 51 +++++++++++++++++++++++++++++----- arch/powerpc/sysdev/indirect_pci.c | 10 ++---- 3 files changed, 54 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h index c0278f0..ffbc5fd 100644 --- a/arch/powerpc/include/asm/pci-bridge.h +++ b/arch/powerpc/include/asm/pci-bridge.h @@ -120,6 +120,12 @@ extern void setup_indirect_pci(struct pci_controller* hose, resource_size_t cfg_addr, resource_size_t cfg_data, u32 flags); +extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val); + +extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 val); + static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) { return bus->sysdata; diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 41bbcc4..9c0fcc9 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -54,12 +54,22 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev) return; } -static int __init fsl_pcie_check_link(struct pci_controller *hose) +static int fsl_indirect_read_config(struct pci_bus *, unsigned int, + int, int, u32 *); + +static int fsl_pcie_check_link(struct pci_controller *hose) { - u32 val; + u32 val = 0; if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { - early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); + if (hose->ops->read == fsl_indirect_read_config) { + struct pci_bus bus; + bus.number = 0; + bus.sysdata = hose; + bus.ops = hose->ops; + indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val); + } else + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); if (val < PCIE_LTSSM_L0) return 1; } else { @@ -74,6 +84,33 @@ static int __init fsl_pcie_check_link(struct pci_controller *hose) return 0; } +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) +{ + struct pci_controller *hose = pci_bus_to_host(bus); + + if (fsl_pcie_check_link(hose)) + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; + else + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; + + return indirect_read_config(bus, devfn, offset, len, val); +} + +static struct pci_ops fsl_indirect_pci_ops = +{ + .read = fsl_indirect_read_config, + .write = indirect_write_config, +}; + +static void __init fsl_setup_indirect_pci(struct pci_controller* hose, + resource_size_t cfg_addr, + resource_size_t cfg_data, u32 flags) +{ + setup_indirect_pci(hose, cfg_addr, cfg_data, flags); + hose->ops = &fsl_indirect_pci_ops; +} + #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) #define MAX_PHYS_ADDR_BITS 40 @@ -469,8 +506,8 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) if (!hose->private_data) goto no_bridge; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, - PPC_INDIRECT_TYPE_BIG_ENDIAN); + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, + PPC_INDIRECT_TYPE_BIG_ENDIAN); if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; @@ -779,8 +816,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev) if (ret) goto err0; } else { - setup_indirect_pci(hose, rsrc_cfg.start, - rsrc_cfg.start + 4, 0); + fsl_setup_indirect_pci(hose, rsrc_cfg.start, + rsrc_cfg.start + 4, 0); } printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index 82fdad8..c6c8b52 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c @@ -20,9 +20,8 @@ #include <asm/pci-bridge.h> #include <asm/machdep.h> -static int -indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 *val) +int indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) { struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; @@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, return PCIBIOS_SUCCESSFUL; } -static int -indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 val) +int indirect_write_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 val) { struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale 2013-03-18 9:22 ` Rojhalat Ibrahim @ 2013-04-03 7:09 ` Rojhalat Ibrahim 2013-04-05 17:37 ` Kumar Gala 0 siblings, 1 reply; 15+ messages in thread From: Rojhalat Ibrahim @ 2013-04-03 7:09 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev Hi Kumar, what about this patch? Any reasons not to apply? Rojhalat On Monday 18 March 2013 10:22:40 Rojhalat Ibrahim wrote: > On Thursday 14 March 2013 15:35:40 Kumar Gala wrote: > > On Mar 14, 2013, at 4:43 AM, Rojhalat Ibrahim wrote: > > > On Wednesday 13 March 2013 14:07:16 Kumar Gala wrote: > > >> diff --git a/arch/powerpc/sysdev/fsl_pci.c > > >> b/arch/powerpc/sysdev/fsl_pci.c > > >> index 41bbcc4..b18c377 100644 > > >> --- a/arch/powerpc/sysdev/fsl_pci.c > > >> +++ b/arch/powerpc/sysdev/fsl_pci.c > > >> @@ -74,6 +74,35 @@ static int __init fsl_pcie_check_link(struct > > >> pci_controller *hose) return 0; > > >> } > > >> > > >> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int > > >> devfn, + int offset, int len, u32 *val) > > >> +{ > > >> + struct pci_controller *hose = pci_bus_to_host(bus); > > >> + > > >> + /* check the link status */ > > >> + if ((bus->number == hose->first_busno) && (devfn == 0)) { > > >> + if (fsl_pcie_check_link(hose)) > > >> + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; > > >> + else > > >> + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; > > >> + } > > >> + return indirect_read_config(bus, devfn, offset, len, val); > > >> +} > > >> + > > > > > > This does not work because fsl_indirect_read_config calls > > > fsl_pcie_check_link which calls early_read_config_dword which eventually > > > calls fsl_indirect_read_config, so the kernel hangs in a recursion loop. > > > Below is a modified patch that does work. > > > > ok, that makes sense, but I guess now its making me question the following statement: > > > if ((bus->number == hose->first_busno) && (devfn == 0)) { > > > > Why do we have this conditional? > > > > - k > > Right. This is not necessary anymore. I modified the patch accordingly. > > > Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de> > --- > arch/powerpc/include/asm/pci-bridge.h | 6 ++++ > arch/powerpc/sysdev/fsl_pci.c | 51 > +++++++++++++++++++++++++++++----- arch/powerpc/sysdev/indirect_pci.c | > 10 ++---- > 3 files changed, 54 insertions(+), 13 deletions(-) > > diff --git a/arch/powerpc/include/asm/pci-bridge.h > b/arch/powerpc/include/asm/pci-bridge.h index c0278f0..ffbc5fd 100644 > --- a/arch/powerpc/include/asm/pci-bridge.h > +++ b/arch/powerpc/include/asm/pci-bridge.h > @@ -120,6 +120,12 @@ extern void setup_indirect_pci(struct pci_controller* > hose, resource_size_t cfg_addr, > resource_size_t cfg_data, u32 flags); > > +extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn, > + int offset, int len, u32 *val); > + > +extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn, > + int offset, int len, u32 val); > + > static inline struct pci_controller *pci_bus_to_host(const struct pci_bus > *bus) { > return bus->sysdata; > diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c > index 41bbcc4..9c0fcc9 100644 > --- a/arch/powerpc/sysdev/fsl_pci.c > +++ b/arch/powerpc/sysdev/fsl_pci.c > @@ -54,12 +54,22 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev) > return; > } > > -static int __init fsl_pcie_check_link(struct pci_controller *hose) > +static int fsl_indirect_read_config(struct pci_bus *, unsigned int, > + int, int, u32 *); > + > +static int fsl_pcie_check_link(struct pci_controller *hose) > { > - u32 val; > + u32 val = 0; > > if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { > - early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); > + if (hose->ops->read == fsl_indirect_read_config) { > + struct pci_bus bus; > + bus.number = 0; > + bus.sysdata = hose; > + bus.ops = hose->ops; > + indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val); > + } else > + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); > if (val < PCIE_LTSSM_L0) > return 1; > } else { > @@ -74,6 +84,33 @@ static int __init fsl_pcie_check_link(struct > pci_controller *hose) return 0; > } > > +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int > devfn, + int offset, int len, u32 *val) > +{ > + struct pci_controller *hose = pci_bus_to_host(bus); > + > + if (fsl_pcie_check_link(hose)) > + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; > + else > + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; > + > + return indirect_read_config(bus, devfn, offset, len, val); > +} > + > +static struct pci_ops fsl_indirect_pci_ops = > +{ > + .read = fsl_indirect_read_config, > + .write = indirect_write_config, > +}; > + > +static void __init fsl_setup_indirect_pci(struct pci_controller* hose, > + resource_size_t cfg_addr, > + resource_size_t cfg_data, u32 flags) > +{ > + setup_indirect_pci(hose, cfg_addr, cfg_data, flags); > + hose->ops = &fsl_indirect_pci_ops; > +} > + > #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) > > #define MAX_PHYS_ADDR_BITS 40 > @@ -469,8 +506,8 @@ int __init fsl_add_bridge(struct platform_device *pdev, > int is_primary) if (!hose->private_data) > goto no_bridge; > > - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, > - PPC_INDIRECT_TYPE_BIG_ENDIAN); > + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, > + PPC_INDIRECT_TYPE_BIG_ENDIAN); > > if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) > hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; > @@ -779,8 +816,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev) > if (ret) > goto err0; > } else { > - setup_indirect_pci(hose, rsrc_cfg.start, > - rsrc_cfg.start + 4, 0); > + fsl_setup_indirect_pci(hose, rsrc_cfg.start, > + rsrc_cfg.start + 4, 0); > } > > printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " > diff --git a/arch/powerpc/sysdev/indirect_pci.c > b/arch/powerpc/sysdev/indirect_pci.c index 82fdad8..c6c8b52 100644 > --- a/arch/powerpc/sysdev/indirect_pci.c > +++ b/arch/powerpc/sysdev/indirect_pci.c > @@ -20,9 +20,8 @@ > #include <asm/pci-bridge.h> > #include <asm/machdep.h> > > -static int > -indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, > - int len, u32 *val) > +int indirect_read_config(struct pci_bus *bus, unsigned int devfn, > + int offset, int len, u32 *val) > { > struct pci_controller *hose = pci_bus_to_host(bus); > volatile void __iomem *cfg_data; > @@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned int > devfn, int offset, return PCIBIOS_SUCCESSFUL; > } > > -static int > -indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, > - int len, u32 val) > +int indirect_write_config(struct pci_bus *bus, unsigned int devfn, > + int offset, int len, u32 val) > { > struct pci_controller *hose = pci_bus_to_host(bus); > volatile void __iomem *cfg_data; > > > _______________________________________________ > Linuxppc-dev mailing list > Linuxppc-dev@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/linuxppc-dev ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale 2013-04-03 7:09 ` Rojhalat Ibrahim @ 2013-04-05 17:37 ` Kumar Gala 2013-04-08 8:15 ` Rojhalat Ibrahim 0 siblings, 1 reply; 15+ messages in thread From: Kumar Gala @ 2013-04-05 17:37 UTC (permalink / raw) To: Rojhalat Ibrahim; +Cc: linuxppc-dev On Apr 3, 2013, at 2:09 AM, Rojhalat Ibrahim wrote: > Hi Kumar, >=20 > what about this patch? Any reasons not to apply? >=20 > Rojhalat Was on vacation, getting back to it now. Do send a proper patch = w/commit message & signed-off-by. - k >=20 >=20 > On Monday 18 March 2013 10:22:40 Rojhalat Ibrahim wrote: >> On Thursday 14 March 2013 15:35:40 Kumar Gala wrote: >>> On Mar 14, 2013, at 4:43 AM, Rojhalat Ibrahim wrote: >>>> On Wednesday 13 March 2013 14:07:16 Kumar Gala wrote: >>>>> diff --git a/arch/powerpc/sysdev/fsl_pci.c >>>>> b/arch/powerpc/sysdev/fsl_pci.c >>>>> index 41bbcc4..b18c377 100644 >>>>> --- a/arch/powerpc/sysdev/fsl_pci.c >>>>> +++ b/arch/powerpc/sysdev/fsl_pci.c >>>>> @@ -74,6 +74,35 @@ static int __init fsl_pcie_check_link(struct >>>>> pci_controller *hose) return 0; >>>>> } >>>>>=20 >>>>> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned = int >>>>> devfn, + int offset, int len, u32 = *val) >>>>> +{ >>>>> + struct pci_controller *hose =3D pci_bus_to_host(bus); >>>>> + >>>>> + /* check the link status */ >>>>> + if ((bus->number =3D=3D hose->first_busno) && (devfn =3D=3D 0)) = { >>>>> + if (fsl_pcie_check_link(hose)) >>>>> + hose->indirect_type |=3D = PPC_INDIRECT_TYPE_NO_PCIE_LINK; >>>>> + else >>>>> + hose->indirect_type &=3D = ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; >>>>> + } >>>>> + return indirect_read_config(bus, devfn, offset, len, val); >>>>> +} >>>>> + >>>>=20 >>>> This does not work because fsl_indirect_read_config calls >>>> fsl_pcie_check_link which calls early_read_config_dword which = eventually >>>> calls fsl_indirect_read_config, so the kernel hangs in a recursion = loop. >>>> Below is a modified patch that does work. >>>=20 >>> ok, that makes sense, but I guess now its making me question the = following=20 > statement: >>>> if ((bus->number =3D=3D hose->first_busno) && (devfn =3D=3D 0)) { >>>=20 >>> Why do we have this conditional? >>>=20 >>> - k >>=20 >> Right. This is not necessary anymore. I modified the patch = accordingly. >>=20 >>=20 >> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de> >> --- >> arch/powerpc/include/asm/pci-bridge.h | 6 ++++ >> arch/powerpc/sysdev/fsl_pci.c | 51 >> +++++++++++++++++++++++++++++----- arch/powerpc/sysdev/indirect_pci.c = |=20 >> 10 ++---- >> 3 files changed, 54 insertions(+), 13 deletions(-) >>=20 >> diff --git a/arch/powerpc/include/asm/pci-bridge.h >> b/arch/powerpc/include/asm/pci-bridge.h index c0278f0..ffbc5fd 100644 >> --- a/arch/powerpc/include/asm/pci-bridge.h >> +++ b/arch/powerpc/include/asm/pci-bridge.h >> @@ -120,6 +120,12 @@ extern void setup_indirect_pci(struct = pci_controller* >> hose, resource_size_t cfg_addr, >> resource_size_t cfg_data, u32 flags); >>=20 >> +extern int indirect_read_config(struct pci_bus *bus, unsigned int = devfn, >> + int offset, int len, u32 *val); >> + >> +extern int indirect_write_config(struct pci_bus *bus, unsigned int = devfn, >> + int offset, int len, u32 val); >> + >> static inline struct pci_controller *pci_bus_to_host(const struct = pci_bus >> *bus) { >> return bus->sysdata; >> diff --git a/arch/powerpc/sysdev/fsl_pci.c = b/arch/powerpc/sysdev/fsl_pci.c >> index 41bbcc4..9c0fcc9 100644 >> --- a/arch/powerpc/sysdev/fsl_pci.c >> +++ b/arch/powerpc/sysdev/fsl_pci.c >> @@ -54,12 +54,22 @@ static void quirk_fsl_pcie_header(struct pci_dev = *dev) >> return; >> } >>=20 >> -static int __init fsl_pcie_check_link(struct pci_controller *hose) >> +static int fsl_indirect_read_config(struct pci_bus *, unsigned int, >> + int, int, u32 *); >> + >> +static int fsl_pcie_check_link(struct pci_controller *hose) >> { >> - u32 val; >> + u32 val =3D 0; >>=20 >> if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { >> - early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); >> + if (hose->ops->read =3D=3D fsl_indirect_read_config) { >> + struct pci_bus bus; >> + bus.number =3D 0; >> + bus.sysdata =3D hose; >> + bus.ops =3D hose->ops; >> + indirect_read_config(&bus, 0, PCIE_LTSSM, 4, = &val); >> + } else >> + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, = &val); >> if (val < PCIE_LTSSM_L0) >> return 1; >> } else { >> @@ -74,6 +84,33 @@ static int __init fsl_pcie_check_link(struct >> pci_controller *hose) return 0; >> } >>=20 >> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned = int >> devfn, + int offset, int len, u32 = *val) >> +{ >> + struct pci_controller *hose =3D pci_bus_to_host(bus); >> + >> + if (fsl_pcie_check_link(hose)) >> + hose->indirect_type |=3D PPC_INDIRECT_TYPE_NO_PCIE_LINK; >> + else >> + hose->indirect_type &=3D = ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; >> + >> + return indirect_read_config(bus, devfn, offset, len, val); >> +} >> + >> +static struct pci_ops fsl_indirect_pci_ops =3D >> +{ >> + .read =3D fsl_indirect_read_config, >> + .write =3D indirect_write_config, >> +}; >> + >> +static void __init fsl_setup_indirect_pci(struct pci_controller* = hose, >> + resource_size_t cfg_addr, >> + resource_size_t cfg_data, u32 = flags) >> +{ >> + setup_indirect_pci(hose, cfg_addr, cfg_data, flags); >> + hose->ops =3D &fsl_indirect_pci_ops; >> +} >> + >> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) >>=20 >> #define MAX_PHYS_ADDR_BITS 40 >> @@ -469,8 +506,8 @@ int __init fsl_add_bridge(struct platform_device = *pdev, >> int is_primary) if (!hose->private_data) >> goto no_bridge; >>=20 >> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, >> - PPC_INDIRECT_TYPE_BIG_ENDIAN); >> + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, >> + PPC_INDIRECT_TYPE_BIG_ENDIAN); >>=20 >> if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) >> hose->indirect_type |=3D = PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; >> @@ -779,8 +816,8 @@ int __init mpc83xx_add_bridge(struct device_node = *dev) >> if (ret) >> goto err0; >> } else { >> - setup_indirect_pci(hose, rsrc_cfg.start, >> - rsrc_cfg.start + 4, 0); >> + fsl_setup_indirect_pci(hose, rsrc_cfg.start, >> + rsrc_cfg.start + 4, 0); >> } >>=20 >> printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " >> diff --git a/arch/powerpc/sysdev/indirect_pci.c >> b/arch/powerpc/sysdev/indirect_pci.c index 82fdad8..c6c8b52 100644 >> --- a/arch/powerpc/sysdev/indirect_pci.c >> +++ b/arch/powerpc/sysdev/indirect_pci.c >> @@ -20,9 +20,8 @@ >> #include <asm/pci-bridge.h> >> #include <asm/machdep.h> >>=20 >> -static int >> -indirect_read_config(struct pci_bus *bus, unsigned int devfn, int = offset, >> - int len, u32 *val) >> +int indirect_read_config(struct pci_bus *bus, unsigned int devfn, >> + int offset, int len, u32 *val) >> { >> struct pci_controller *hose =3D pci_bus_to_host(bus); >> volatile void __iomem *cfg_data; >> @@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned = int >> devfn, int offset, return PCIBIOS_SUCCESSFUL; >> } >>=20 >> -static int >> -indirect_write_config(struct pci_bus *bus, unsigned int devfn, int = offset, >> - int len, u32 val) >> +int indirect_write_config(struct pci_bus *bus, unsigned int devfn, >> + int offset, int len, u32 val) >> { >> struct pci_controller *hose =3D pci_bus_to_host(bus); >> volatile void __iomem *cfg_data; >>=20 >>=20 >> _______________________________________________ >> Linuxppc-dev mailing list >> Linuxppc-dev@lists.ozlabs.org >> https://lists.ozlabs.org/listinfo/linuxppc-dev ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale 2013-04-05 17:37 ` Kumar Gala @ 2013-04-08 8:15 ` Rojhalat Ibrahim 2013-04-10 15:18 ` Kumar Gala 0 siblings, 1 reply; 15+ messages in thread From: Rojhalat Ibrahim @ 2013-04-08 8:15 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev Up to now the PCIe link status on Freescale PCIe controllers was only checked once at boot time. So hotplug did not work. With this patch the link status is checked on every config read. PCIe devices not present at boot time are found after doing 'echo 1 >/sys/bus/pci/rescan'. Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de> --- arch/powerpc/include/asm/pci-bridge.h | 6 ++++ arch/powerpc/sysdev/fsl_pci.c | 51 +++++++++++++++++++++++++++++----- arch/powerpc/sysdev/indirect_pci.c | 10 ++---- 3 files changed, 54 insertions(+), 13 deletions(-) diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h index c0278f0..ffbc5fd 100644 --- a/arch/powerpc/include/asm/pci-bridge.h +++ b/arch/powerpc/include/asm/pci-bridge.h @@ -120,6 +120,12 @@ extern void setup_indirect_pci(struct pci_controller* hose, resource_size_t cfg_addr, resource_size_t cfg_data, u32 flags); +extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val); + +extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 val); + static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) { return bus->sysdata; diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 83918c3..82e3317 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -54,12 +54,22 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev) return; } -static int __init fsl_pcie_check_link(struct pci_controller *hose) +static int fsl_indirect_read_config(struct pci_bus *, unsigned int, + int, int, u32 *); + +static int fsl_pcie_check_link(struct pci_controller *hose) { - u32 val; + u32 val = 0; if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { - early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); + if (hose->ops->read == fsl_indirect_read_config) { + struct pci_bus bus; + bus.number = 0; + bus.sysdata = hose; + bus.ops = hose->ops; + indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val); + } else + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); if (val < PCIE_LTSSM_L0) return 1; } else { @@ -74,6 +84,33 @@ static int __init fsl_pcie_check_link(struct pci_controller *hose) return 0; } +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) +{ + struct pci_controller *hose = pci_bus_to_host(bus); + + if (fsl_pcie_check_link(hose)) + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; + else + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; + + return indirect_read_config(bus, devfn, offset, len, val); +} + +static struct pci_ops fsl_indirect_pci_ops = +{ + .read = fsl_indirect_read_config, + .write = indirect_write_config, +}; + +static void __init fsl_setup_indirect_pci(struct pci_controller* hose, + resource_size_t cfg_addr, + resource_size_t cfg_data, u32 flags) +{ + setup_indirect_pci(hose, cfg_addr, cfg_data, flags); + hose->ops = &fsl_indirect_pci_ops; +} + #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) #define MAX_PHYS_ADDR_BITS 40 @@ -469,8 +506,8 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary) if (!hose->private_data) goto no_bridge; - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, - PPC_INDIRECT_TYPE_BIG_ENDIAN); + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, + PPC_INDIRECT_TYPE_BIG_ENDIAN); if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; @@ -779,8 +816,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev) if (ret) goto err0; } else { - setup_indirect_pci(hose, rsrc_cfg.start, - rsrc_cfg.start + 4, 0); + fsl_setup_indirect_pci(hose, rsrc_cfg.start, + rsrc_cfg.start + 4, 0); } printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c index 82fdad8..c6c8b52 100644 --- a/arch/powerpc/sysdev/indirect_pci.c +++ b/arch/powerpc/sysdev/indirect_pci.c @@ -20,9 +20,8 @@ #include <asm/pci-bridge.h> #include <asm/machdep.h> -static int -indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 *val) +int indirect_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) { struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; @@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, return PCIBIOS_SUCCESSFUL; } -static int -indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, - int len, u32 val) +int indirect_write_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 val) { struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; --- 1.8.1.5 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale 2013-04-08 8:15 ` Rojhalat Ibrahim @ 2013-04-10 15:18 ` Kumar Gala 0 siblings, 0 replies; 15+ messages in thread From: Kumar Gala @ 2013-04-10 15:18 UTC (permalink / raw) To: Rojhalat Ibrahim; +Cc: linuxppc-dev On Apr 8, 2013, at 3:15 AM, Rojhalat Ibrahim wrote: > Up to now the PCIe link status on Freescale PCIe controllers was only > checked once at boot time. So hotplug did not work. With this patch = the > link status is checked on every config read. PCIe devices not present = at > boot time are found after doing 'echo 1 >/sys/bus/pci/rescan'. >=20 > Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de> > --- > arch/powerpc/include/asm/pci-bridge.h | 6 ++++ > arch/powerpc/sysdev/fsl_pci.c | 51 = +++++++++++++++++++++++++++++----- > arch/powerpc/sysdev/indirect_pci.c | 10 ++---- > 3 files changed, 54 insertions(+), 13 deletions(-) >=20 > diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/pow applied to next - k= ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in 2013-03-13 19:07 [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in Kumar Gala 2013-03-13 19:07 ` [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale Kumar Gala @ 2013-04-08 8:20 ` Rojhalat Ibrahim 2013-04-10 15:17 ` Kumar Gala 2013-04-15 5:42 ` [PATCH] powerpc: fix usage of setup_pci_atmu() Michael Neuling 3 siblings, 0 replies; 15+ messages in thread From: Rojhalat Ibrahim @ 2013-04-08 8:20 UTC (permalink / raw) To: linuxppc-dev On Wednesday 13 March 2013 14:07:15 Kumar Gala wrote: > Move to keeping the SoC registers that control and config the PCI > controllers on FSL SoCs in the pci_controller struct. This allows us to > not need to ioremap() the registers in multiple different places that > use them. > > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Rojhalat Ibrahim <imr@rtschenk.de> > --- > arch/powerpc/include/asm/pci-bridge.h | 5 ++- > arch/powerpc/sysdev/fsl_pci.c | 69 > ++++++++++++++------------------- 2 files changed, 34 insertions(+), 40 > deletions(-) > > diff --git a/arch/powerpc/include/asm/pci-bridge.h > b/arch/powerpc/include/asm/pci-bridge.h index 025a130..c0278f0 100644 > --- a/arch/powerpc/include/asm/pci-bridge.h > +++ b/arch/powerpc/include/asm/pci-bridge.h > @@ -70,6 +70,8 @@ struct pci_controller { > * BIG_ENDIAN - cfg_addr is a big endian register > * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on > * the PLB4. Effectively disable MRM commands by setting this. > + * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe > + * link status is in a RC PCIe cfg register (vs being a SoC register) > */ > #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 > #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 > @@ -77,6 +79,7 @@ struct pci_controller { > #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 > #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 > #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 > +#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040 > u32 indirect_type; > /* Currently, we limit ourselves to 1 IO range and 3 mem > * ranges since the common pci_bus structure can't handle more > @@ -90,9 +93,9 @@ struct pci_controller { > > #ifdef CONFIG_PPC64 > unsigned long buid; > +#endif /* CONFIG_PPC64 */ > > void *private_data; > -#endif /* CONFIG_PPC64 */ > }; > > /* These are used for config access before all the PCI probing > diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c > index 3271177..41bbcc4 100644 > --- a/arch/powerpc/sysdev/fsl_pci.c > +++ b/arch/powerpc/sysdev/fsl_pci.c > @@ -54,34 +54,22 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev) > return; > } > > -static int __init fsl_pcie_check_link(struct pci_controller *hose, > - struct resource *rsrc) > +static int __init fsl_pcie_check_link(struct pci_controller *hose) > { > - struct ccsr_pci __iomem *pci = NULL; > u32 val; > > - /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ > - if (rsrc) { > - pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", > - (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); > - pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); > - if (!pci) { > - dev_err(hose->parent, "Unable to map PCIe registers\n"); > - return -ENOMEM; > - } > - if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_3_0) { > - val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) > - >> PEX_CSR0_LTSSM_SHIFT; > - if (val != PEX_CSR0_LTSSM_L0) > - return 1; > - iounmap(pci); > - return 0; > - } > - iounmap(pci); > + if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { > + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); > + if (val < PCIE_LTSSM_L0) > + return 1; > + } else { > + struct ccsr_pci __iomem *pci = hose->private_data; > + /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ > + val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) > + >> PEX_CSR0_LTSSM_SHIFT; > + if (val != PEX_CSR0_LTSSM_L0) > + return 1; > } > - early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); > - if (val < PCIE_LTSSM_L0) > - return 1; > > return 0; > } > @@ -148,10 +136,9 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci, > } > > /* atmu setup for fsl pci/pcie controller */ > -static void setup_pci_atmu(struct pci_controller *hose, > - struct resource *rsrc) > +static void setup_pci_atmu(struct pci_controller *hose) > { > - struct ccsr_pci __iomem *pci; > + struct ccsr_pci __iomem *pci = hose->private_data; > int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; > u64 mem, sz, paddr_hi = 0; > u64 paddr_lo = ULLONG_MAX; > @@ -162,15 +149,6 @@ static void setup_pci_atmu(struct pci_controller *hose, > const u64 *reg; > int len; > > - pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", > - (u64)rsrc->start, (u64)resource_size(rsrc)); > - > - pci = ioremap(rsrc->start, resource_size(rsrc)); > - if (!pci) { > - dev_err(hose->parent, "Unable to map ATMU registers\n"); > - return; > - } > - > if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { > if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { > win_idx = 2; > @@ -451,6 +429,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, > int is_primary) const int *bus_range; > u8 hdr_type, progif; > struct device_node *dev; > + struct ccsr_pci __iomem *pci; > > dev = pdev->dev.of_node; > > @@ -483,9 +462,19 @@ int __init fsl_add_bridge(struct platform_device *pdev, > int is_primary) hose->first_busno = bus_range ? bus_range[0] : 0x0; > hose->last_busno = bus_range ? bus_range[1] : 0xff; > > + pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", > + (u64)rsrc.start, (u64)resource_size(&rsrc)); > + > + pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); > + if (!hose->private_data) > + goto no_bridge; > + > setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, > PPC_INDIRECT_TYPE_BIG_ENDIAN); > > + if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) > + hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; > + > if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { > /* For PCIE read HEADER_TYPE to identify controler mode */ > early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); > @@ -505,7 +494,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, > int is_primary) if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { > hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | > PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; > - if (fsl_pcie_check_link(hose, &rsrc)) > + if (fsl_pcie_check_link(hose)) > hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; > } > > @@ -522,11 +511,12 @@ int __init fsl_add_bridge(struct platform_device > *pdev, int is_primary) pci_process_bridge_OF_ranges(hose, dev, is_primary); > > /* Setup PEX window registers */ > - setup_pci_atmu(hose, &rsrc); > + setup_pci_atmu(hose); > > return 0; > > no_bridge: > + iounmap(hose->private_data); > /* unmap cfg_data & cfg_addr separately if not on same page */ > if (((unsigned long)hose->cfg_data & PAGE_MASK) != > ((unsigned long)hose->cfg_addr & PAGE_MASK)) > @@ -703,11 +693,12 @@ static int __init mpc83xx_pcie_setup(struct > pci_controller *hose, WARN_ON(hose->dn->data); > hose->dn->data = pcie; > hose->ops = &mpc83xx_pcie_ops; > + hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; > > out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); > out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); > > - if (fsl_pcie_check_link(hose, NULL)) > + if (fsl_pcie_check_link(hose)) > hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; > > return 0; ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in 2013-03-13 19:07 [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in Kumar Gala 2013-03-13 19:07 ` [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale Kumar Gala 2013-04-08 8:20 ` [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in Rojhalat Ibrahim @ 2013-04-10 15:17 ` Kumar Gala 2013-04-15 5:42 ` [PATCH] powerpc: fix usage of setup_pci_atmu() Michael Neuling 3 siblings, 0 replies; 15+ messages in thread From: Kumar Gala @ 2013-04-10 15:17 UTC (permalink / raw) To: linuxppc-dev On Mar 13, 2013, at 2:07 PM, Kumar Gala wrote: > Move to keeping the SoC registers that control and config the PCI > controllers on FSL SoCs in the pci_controller struct. This allows us = to > not need to ioremap() the registers in multiple different places that > use them. >=20 > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > --- > arch/powerpc/include/asm/pci-bridge.h | 5 ++- > arch/powerpc/sysdev/fsl_pci.c | 69 = ++++++++++++++------------------- > 2 files changed, 34 insertions(+), 40 deletions(-) applied to next - k= ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH] powerpc: fix usage of setup_pci_atmu() 2013-03-13 19:07 [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in Kumar Gala ` (2 preceding siblings ...) 2013-04-10 15:17 ` Kumar Gala @ 2013-04-15 5:42 ` Michael Neuling 2013-04-15 16:30 ` Kim Phillips 2013-04-29 23:06 ` Stephen Rothwell 3 siblings, 2 replies; 15+ messages in thread From: Michael Neuling @ 2013-04-15 5:42 UTC (permalink / raw) To: Kumar Gala, sfr; +Cc: linuxppc-dev, linux-next Linux next is currently failing to compile mpc85xx_defconfig with: arch/powerpc/sysdev/fsl_pci.c:944:2: error: too many arguments to function 'setup_pci_atmu' This is caused by (from Kumar's next branch): commit 34642bbb3d12121333efcf4ea7dfe66685e403a1 Author: Kumar Gala <galak@kernel.crashing.org> powerpc/fsl-pci: Keep PCI SoC controller registers in pci_controller Which changed definition of setup_pci_atmu() but didn't update one of the callers. Below fixes this. Signed-off-by: Michael Neuling <mikey@neuling.org> --- Kumar: this is for your next tree diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 83918c3..a10a036 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -941,7 +941,7 @@ static int fsl_pci_resume(struct device *dev) return -ENODEV; } - setup_pci_atmu(hose, &pci_rsrc); + setup_pci_atmu(hose); return 0; } ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH] powerpc: fix usage of setup_pci_atmu() 2013-04-15 5:42 ` [PATCH] powerpc: fix usage of setup_pci_atmu() Michael Neuling @ 2013-04-15 16:30 ` Kim Phillips 2013-04-29 23:06 ` Stephen Rothwell 1 sibling, 0 replies; 15+ messages in thread From: Kim Phillips @ 2013-04-15 16:30 UTC (permalink / raw) To: Michael Neuling; +Cc: sfr, linux-next, linuxppc-dev On Mon, 15 Apr 2013 15:42:01 +1000 Michael Neuling <mikey@neuling.org> wrote: > Linux next is currently failing to compile mpc85xx_defconfig with: > arch/powerpc/sysdev/fsl_pci.c:944:2: error: too many arguments to function 'setup_pci_atmu' > > This is caused by (from Kumar's next branch): > commit 34642bbb3d12121333efcf4ea7dfe66685e403a1 > Author: Kumar Gala <galak@kernel.crashing.org> > powerpc/fsl-pci: Keep PCI SoC controller registers in pci_controller > > Which changed definition of setup_pci_atmu() but didn't update one of > the callers. Below fixes this. > > Signed-off-by: Michael Neuling <mikey@neuling.org> > --- > Kumar: this is for your next tree Reviewed-by: Kim Phillips <kim.phillips@freescale.com> Thanks, Kim ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] powerpc: fix usage of setup_pci_atmu() 2013-04-15 5:42 ` [PATCH] powerpc: fix usage of setup_pci_atmu() Michael Neuling 2013-04-15 16:30 ` Kim Phillips @ 2013-04-29 23:06 ` Stephen Rothwell 2013-04-30 1:08 ` Benjamin Herrenschmidt 1 sibling, 1 reply; 15+ messages in thread From: Stephen Rothwell @ 2013-04-29 23:06 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev, Michael Neuling, linux-next [-- Attachment #1: Type: text/plain, Size: 1209 bytes --] Hi Kumar, On Mon, 15 Apr 2013 15:42:01 +1000 Michael Neuling <mikey@neuling.org> wrote: > > Linux next is currently failing to compile mpc85xx_defconfig with: > arch/powerpc/sysdev/fsl_pci.c:944:2: error: too many arguments to function 'setup_pci_atmu' > > This is caused by (from Kumar's next branch): > commit 34642bbb3d12121333efcf4ea7dfe66685e403a1 > Author: Kumar Gala <galak@kernel.crashing.org> > powerpc/fsl-pci: Keep PCI SoC controller registers in pci_controller > > Which changed definition of setup_pci_atmu() but didn't update one of > the callers. Below fixes this. > > Signed-off-by: Michael Neuling <mikey@neuling.org> > --- > Kumar: this is for your next tree > > diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c > index 83918c3..a10a036 100644 > --- a/arch/powerpc/sysdev/fsl_pci.c > +++ b/arch/powerpc/sysdev/fsl_pci.c > @@ -941,7 +941,7 @@ static int fsl_pci_resume(struct device *dev) > return -ENODEV; > } > > - setup_pci_atmu(hose, &pci_rsrc); > + setup_pci_atmu(hose); > > return 0; > } > This is still not in your tree ... -- Cheers, Stephen Rothwell sfr@canb.auug.org.au [-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] powerpc: fix usage of setup_pci_atmu() 2013-04-29 23:06 ` Stephen Rothwell @ 2013-04-30 1:08 ` Benjamin Herrenschmidt 0 siblings, 0 replies; 15+ messages in thread From: Benjamin Herrenschmidt @ 2013-04-30 1:08 UTC (permalink / raw) To: Stephen Rothwell; +Cc: linuxppc-dev, Michael Neuling, linux-next On Tue, 2013-04-30 at 09:06 +1000, Stephen Rothwell wrote: > > This is still not in your tree ... I'll apply it after I merge kumar stuff. Cheers, Ben. ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2013-04-30 1:08 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-03-13 19:07 [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in Kumar Gala 2013-03-13 19:07 ` [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale Kumar Gala 2013-03-14 9:43 ` Rojhalat Ibrahim 2013-03-14 20:35 ` Kumar Gala 2013-03-18 9:22 ` Rojhalat Ibrahim 2013-04-03 7:09 ` Rojhalat Ibrahim 2013-04-05 17:37 ` Kumar Gala 2013-04-08 8:15 ` Rojhalat Ibrahim 2013-04-10 15:18 ` Kumar Gala 2013-04-08 8:20 ` [RFC][PATCH 1/2] powerpc/fsl-pci: Keep PCI SoC controller registers in Rojhalat Ibrahim 2013-04-10 15:17 ` Kumar Gala 2013-04-15 5:42 ` [PATCH] powerpc: fix usage of setup_pci_atmu() Michael Neuling 2013-04-15 16:30 ` Kim Phillips 2013-04-29 23:06 ` Stephen Rothwell 2013-04-30 1:08 ` Benjamin Herrenschmidt
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