From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from tsinghua.org.cn (mail.tsinghua.org.cn [210.77.143.232]) by ozlabs.org (Postfix) with SMTP id A4133DDF20 for ; Wed, 12 Mar 2008 19:48:25 +1100 (EST) Message-ID: <405310403.22207@tsinghua.org.cn> From: "=?gb2312?B?ufm+og==?=" To: support.asia@freescale.com Date: Wed, 12 Mar 2008 16:26:43 +0800 Message-ID: Subject: the question about the internet checksum and CRC on MPC8360? Content-Type: text/plain Cc: linuxppc-embedded@ozlabs.org Reply-To: =?gb2312?B?ufm+og==?= List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Hi,freescale, Whether or not the checksum is checked and generated by hardware on QE? We read the linux kernel code, found that the chechsum is dealed by software, is it true? How can we let the hardware to deal with the checksum and CRC? then maybe the speed of TCP package will fast. follow is from the MPC8360ERM document: The UEC may programmed to check IP header checksum on the receiver, and generate IP header checksum on the transmitter.