From: Ralph Siemsen <rsiemsen@rossvideo.com>
To: James Perkins <james@loowit.net>
Cc: linuxppc-dev@lists.linuxppc.org
Subject: Re: early UART mapping in head_44x.S
Date: Tue, 13 Jul 2004 18:48:37 -0400 [thread overview]
Message-ID: <40F466C5.5010202@rossvideo.com> (raw)
In-Reply-To: <40F4621F.1000206@loowit.net>
James Perkins wrote:
> ori won't clear the invalid bits, it just "or"s in the TS bit itself.
> What suprises me is that TLB 1 is being written twice. It may make more
> sense to change the second case
>
> li r0,1 /* TLB slot 1 */
>
> to
> li r0,2 /* TLB slot 2 */
>
> So that there is both a TS=0 and a TS=1 mapping, in TLB entry index 1
> and 2, respectively -- this will catch both the MSR[DS]=0 and MSR[DS]=1
> cases.
Yes I see now. Your suggestion also works, and it seems more logical -
though I doubt anything in the early startup would ever do an access in
TS=1 virtual space... shortly after this the real MMU init is done and
it will overwrite all of these temporary mappings...
-Ralph
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next prev parent reply other threads:[~2004-07-13 22:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-07-13 21:23 early UART mapping in head_44x.S Ralph Siemsen
2004-07-13 21:51 ` Ralph Siemsen
2004-07-13 22:28 ` James Perkins
2004-07-13 22:48 ` Ralph Siemsen [this message]
2004-07-22 23:55 ` Matt Porter
-- strict thread matches above, loose matches on Subject: below --
2004-08-02 12:30 Daren Hayward
2004-08-02 13:57 ` Matt Porter
2004-08-03 17:58 ` Ralph Siemsen
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