From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40zxg45535zF0dT for ; Tue, 5 Jun 2018 00:10:56 +1000 (AEST) In-Reply-To: <20180511061303.10728-2-alastair@au1.ibm.com> To: "Alastair D'Silva" , linuxppc-dev@lists.ozlabs.org From: Michael Ellerman Cc: mikey@neuling.org, arnd@arndb.de, linux-doc@vger.kernel.org, malat@debian.org, gregkh@linuxfoundation.org, corbet@lwn.net, vaibhav@linux.vnet.ibm.com, npiggin@gmail.com, linux-kernel@vger.kernel.org, fbarrat@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com, andrew.donnellan@au1.ibm.com, pombredanne@nexb.com, felix@linux.vnet.ibm.com, sukadev@linux.vnet.ibm.com, Alastair D'Silva Subject: Re: [v5,1/7] powerpc: Add TIDR CPU feature for POWER9 Message-Id: <40zxg24KjVz9s0w@ozlabs.org> Date: Tue, 5 Jun 2018 00:10:53 +1000 (AEST) List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Fri, 2018-05-11 at 06:12:57 UTC, "Alastair D'Silva" wrote: > From: Alastair D'Silva > > This patch adds a CPU feature bit to show whether the CPU has > the TIDR register available, enabling as_notify/wait in userspace. > > Signed-off-by: Alastair D'Silva > Reviewed-by: Frederic Barrat > Reviewed-by: Andrew Donnellan Series applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/819844285ef2b5d15466f5b5062514 cheers