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Date: Tue, 03 May 2005 11:14:39 -0700
From: Conn Clark <clark@esteem.com>
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To: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
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Cc: linuxppc-embedded@ozlabs.org
Subject: Re: CONFIG_PIN_TLB experiments
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Marcelo Tosatti wrote:
> Hi 8xx folks,

<SNIP>

> 
> Actually, CONFIG_PIN_TLB slowdowns the system, as expected (there are only 
> 28 usable TLB's instead of 32).
> 
> 
> v2.6 CONFIG_PIN_TLB:
> I-TLB userspace misses: 162113
> I-TLB kernel misses: 135911
> D-TLB userspace misses: 289452
> D-TLB kernel misses: 257039
> 
> v2.6 without CONFIG_PIN_TLB:
> I-TLB userspace misses: 160828
> I-TLB kernel misses: 134746
> D-TLB userspace misses: 253557
> D-TLB kernel misses: 227383
> 
> 

Considering that the TLB kernel misses are higher with tlb pinning it 
appears as though the pinned TLBs are not marked as valid.


> The following BDI output shows the pinned, 8MByte data page mapping present,
> at 0xc0000000.
> 
> BDI>rds 826
> SPR  826 : 0x00007f00        32512
> BDI>rms 792 0x0c001C00
> BDI>rms 824 1
> BDI>rds 824
> SPR  824 : 0xc00000f0  -1073741584
> BDI>rds 825
> SPR  825 : 0x00000fe0         4064
> BDI>rds 826
> SPR  826 : 0x00007fff        32767       <- "0x00007fff" was 0x00007f00" initially. 
> 				             I tried enabling usermode access without
> 					     success.
> 
> There are several 4Kb mappings inside the range covered by this 8Mb TLB entry, 
> for example: 
> 
> BDI>rms 792 0x0c000200
> BDI>rms 824 1
> BDI>rds 824
> SPR  824 : 0xc0224f17  -1071493353
> BDI>rds 825
> SPR  825 : 0x002241e0      2245088
> BDI>rds 826
> SPR  826 : 0x00007f00        32512
> 
> And more, without so much detail:
> SPR  824 : 0xc0224f17  -1071493353
> SPR  824 : 0xc01fbf17  -1071661289
> SPR  824 : 0xc0246f17  -1071354089
> SPR  824 : 0xc023ff17  -1071382761
> SPR  824 : 0xc7e35f17  - 941400297
> SPR  824 : 0xc0244f17  -1071362281
> SPR  824 : 0xc023ef17  -1071386857
> 
> Note that protection (SPR 826) is exactly the same as the 8Mbyte page protection. 
> 
> Why is the translation mechanism rejection the pinned mappings? 
> 
> Dan, have you ever seen this work? Am I misunderstanding how the pinned
> entries are supposed to work? 

When you load the Mx_EPN of the pinned area is the EV bit being set?


> 
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> 


-- Conn

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Conn Clark
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Electronic Systems Technology Inc.        www.esteem.com

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