From: David Hawkins <dwh@ovro.caltech.edu>
To: linuxppc-embedded@ozlabs.org
Subject: Yosemite/440EP PLB4 vs PLB3 DMA to PCI issue
Date: Sat, 04 Feb 2006 20:41:38 -0800 [thread overview]
Message-ID: <43E58202.8020000@ovro.caltech.edu> (raw)
In-Reply-To: <20060202111603.B28536@cox.net>
Hi all,
I've been testing the PLB4 and PLB3 DMA controllers
for memory-to-memory transfers between the Yosemite
board SDRAM and a PCI board.
The PCI board contains a PLX PCI-9054 PCI controller
(PCI-to-local bus bridge), and the board contains
SDRAM at the addresses I was testing DMA.
So, the test is basically:
Yosemite SDRAM <-> 440EP bridge <-> PLX-9054 bridge <-> SDRAM
Here's the problem/issue:
PLB4 burst DMA reads are performed as blocks of 32-bytes
(8 transfers of 4-bytes), with the PCI command code
toggling between memory-read-multiple (MRM) and
then memory-read-line (MRL). The change in PCI command
code causes the PLX-9054 controller to consider each
32-byte burst to be a new transaction, and hence
it flushes its internal read FIFO and disconnects from
the local bus for each burst.
The PLB3 DMA controller does not do this, it always
bursts using a memory-read-line (MRL) PCI command code.
Hence the PLX-9054 can determine that the next 32-byte
burst follows on from the previous, and it can deliver
data from its internal FIFOs.
The performance results for transfers between the
Yosemite SDRAM and a device on the 33MHz/32-bit PCI bus were;
DMA controller Read Write
-------------- ---- -----
PLB4 19.9MB/s 46.5MB/s
PLB3 46.0MB/s 46.7MB/s
For the curious, here is the section from my test doc
containing logic analyzer traces;
http://www.ovro.caltech.edu/~dwh/yosemite_440ep_dma.pdf
The performance is below that of the maximum 132MB/s
achievable on the PCI bus. But since the DMA controllers
on the 440EP have to first read and then write,
I don't expect the DMA to do much better than 60MB/s.
So, the ~50MB/s I observed for the majority of tests
seems pretty reasonable.
I haven't had a chance to look at the 440EP PCI bridge
configuration registers that might lead to the use of the
MRM/MRL commands. I'll do that next. I just figured I'd
post these results now, so that others reading this
list might comment (Stefan from Denx comes to mind :))
Cheers
Dave
next prev parent reply other threads:[~2006-02-05 4:39 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-02-02 9:35 Yosemite/440EP why are readl()/ioread32() setup to readlittle-endian? Jenkins, Clive
2006-02-02 9:46 ` Eugene Surovegin
2006-02-02 14:37 ` Matt Porter
2006-02-02 17:45 ` Eugene Surovegin
2006-02-02 18:16 ` Matt Porter
2006-02-05 4:41 ` David Hawkins [this message]
2006-02-05 10:39 ` Yosemite/440EP PLB4 vs PLB3 DMA to PCI issue Wolfgang Denk
2006-02-05 23:47 ` David Hawkins
2006-02-06 18:31 ` Stefan Roese
2006-02-06 19:09 ` David Hawkins
2006-02-08 15:38 ` Stefan Roese
2006-02-08 18:43 ` David Hawkins
2006-02-09 0:34 ` Wolfgang Denk
2006-02-09 13:25 ` Mark Chambers
2006-02-09 23:58 ` Yosemite/440EP 'issues' as a PCI target David Hawkins
2006-02-10 7:47 ` Stefan Roese
2006-02-10 17:05 ` David Hawkins
2006-02-10 17:20 ` Andrew Armitage
2006-02-10 17:26 ` David Hawkins
2006-02-10 17:31 ` Wolfgang Denk
2006-02-10 17:38 ` David Hawkins
2006-02-10 17:58 ` David Hawkins
2006-02-11 6:03 ` David Hawkins
2006-02-11 8:21 ` Stefan Roese
2006-02-11 18:15 ` David Hawkins
2006-02-11 13:03 ` Wolfgang Denk
2006-02-10 17:59 ` Stefan Roese
2006-02-10 18:11 ` David Hawkins
2006-02-11 8:06 ` Stefan Roese
2006-02-11 18:06 ` David Hawkins
2006-02-11 19:00 ` David Hawkins
[not found] ` <43ECCCA2.1070007@sandburst.com>
[not found] ` <43ECCE7A.4090507@ovro.caltech.edu>
[not found] ` <43ECD19E.8010604@sandburst.com>
2006-02-10 19:13 ` David Hawkins
[not found] ` <001701c62e6c$09c48ea0$6401a8c0@CHUCK2>
2006-02-10 18:19 ` David Hawkins
2006-02-11 6:06 ` David Hawkins
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