Re: Yosemite/440EP 'issues' as a PCI target

[David Hawkins <dwh@ovro.caltech.edu>]

Hi Mark,

> Some unsolicited brainstorming

Brainstorm away!

> if you go with a QUICC based processor you could bring 
> the data into SDRAM via a serial port. That gets you DMA
> and some extra buffer management help from the co-processor.

Ooooh I like it.

> Some extra logic in the FPGA (but less pins), but you've got
> a lot of flexibility in what you can do with SCCs or I2C.

But do I have the bandwidth? (I'll look in the data book).

> I'm currently working on an MPC8247 based design, btw.
> It has a PC104+ header and is directly connected to a 
> T.I. 6205 (which, at $10, is a lot of crunch for the buck).

But the you have to program it with Code Composer and
the horrid TI DSP tools. Yeah, ok I've got the older
C31 version, not the newer 6x-based DSPs. I'm trying
to move the system to Linux, so that others round
here can 'share the burden'. I'm designing the boards,
drivers, and host software (ACE/C++) at the moment.
I need a break! :)

I want to avoid spending $20k on the TI tools and an
emulator ... hey, call me cheap.

However, I like the SCC idea. They sound very similar
to the multi-processor links on the Analog Devices
SHARC DSPs.

More reading :)

Dave