From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: In-Reply-To: References: <20070905192116.GH32113@ld0162-tx32.am.freescale.net>, <20070907005803.GJ26079@localhost.localdomain> Mime-Version: 1.0 (Apple Message framework v623) Content-Type: text/plain; charset=US-ASCII; format=flowed Message-Id: <43ccd497fa7fa1f647ea2e3ca8168793@kernel.crashing.org> From: Segher Boessenkool Subject: Re: [PATCH 08/10] bootwrapper: Add a firmware-independent "raw" target. Date: Mon, 10 Sep 2007 23:17:00 +0200 To: Milton Miller Cc: ppcdev , David Gibson List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , >>> +static inline void disable_irq(void) >>> +{ >>> + int dummy; >>> + asm volatile("mfmsr %0; rlwinm %0, %0, 0, ~(1<<15); mtmsr %0" >>> : >>> + "=r" (dummy) : : "memory"); >>> +} > > This will fail (mtmsr illegal instruction) on 64 bit processors that do > not implement the bridge facility (POWER4, 5, 6, PPC970, ...) The latest ISA lists mtmsr as non-optional, not part of the bridge facility. That suggests that all CPUs do in fact implement it. 970 does implement the 64-bit bridge facility, btw (well, "most of it"). Segher