From: "David Baird" <dhbaird@gmail.com>
To: linuxppc-embedded@ozlabs.org
Subject: Re: TLB Miss booting linux kernel on ppc 405
Date: Wed, 13 Feb 2008 10:51:05 -0700 [thread overview]
Message-ID: <440abda90802130951h7a23743asc85454bf089c7e55@mail.gmail.com> (raw)
In-Reply-To: <5ee408090802130938u7d069636g42a496e489fe5b80@mail.gmail.com>
On Feb 13, 2008 10:38 AM, Ricardo Ayres Severo <severo.ricardo@gmail.com> wrote:
> I tracked the kernel execution using step one instruction (si) on gdb
> and matching the jumps with the System.map.
> It is a Data TLB Miss and this is the register dump after the miss occurs:
>
> r1: 00502090
> r2: 0000000f
> r3: c00003c0
> r4: c0000000
> r5: 00000000
> r6: 00000000
> r7: 74747955
> r8: 4c302c39
> r9: 00000000
> pc: 00001100
> lr: 00000018
Can you also past the special registers (srrd in XMD)? I am very
curious about SRR0 and SRR1 and maybe some of the others.
> Now I'm checking the PPC cache configurations on XPS, because when
> treating the DTLB Miss Exception a Machine Check Exception occurs when
> it works with L1. Does this makes sense or am I confusing things?
Too soon for me to tell :-)
next prev parent reply other threads:[~2008-02-13 17:51 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-02-13 16:50 TLB Miss booting linux kernel on ppc 405 Ricardo Ayres Severo
2008-02-13 17:17 ` David Baird
2008-02-13 17:38 ` Ricardo Ayres Severo
2008-02-13 17:51 ` David Baird [this message]
2008-02-13 18:03 ` Ricardo Ayres Severo
2008-02-13 18:32 ` David Baird
2008-02-13 18:49 ` Ricardo Ayres Severo
2008-02-13 19:02 ` David Baird
2008-02-20 21:24 ` Robert Woodworth
2008-02-20 21:29 ` Ricardo Ayres Severo
2008-02-20 21:47 ` David Baird
2008-02-21 17:50 ` Ricardo Ayres Severo
2008-02-21 18:00 ` David Baird
2008-02-21 18:04 ` David Baird
2008-02-21 19:12 ` Robert Woodworth
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