From: Peter Ryser <peter.ryser@xilinx.com>
To: Aidan Williams <aidan@nicta.com.au>
Cc: Anantharaman Chetan-W16155 <Chetan.S.Anantharaman@motorola.com>,
linuxppc-embedded@ozlabs.org
Subject: Re: Linux 2.4 Kernel on Xilinx Virtex4 FX100's PPC
Date: Thu, 01 Jun 2006 10:05:12 -0700 [thread overview]
Message-ID: <447F1E48.10808@xilinx.com> (raw)
In-Reply-To: <447E1725.4010908@nicta.com.au>
There are some silicon issues on the PPC405 in V4 with PVR 0x20011430=20
which are documented in Xilinx solution record 20658. All these issues=20
are fixed in silicon where the PPC405 has a PVR of 0x20011470.
Said that it's not true that the caches cannot be used in silicon with=20
PVR 0x20011430. The problem is a corner case which does not show in=20
typical designs.
- Peter
Aidan Williams wrote:
>Anantharaman Chetan-W16155 wrote:
> =20
>
>>Has anyone successfully ported a Linux 2.4 Kernel on a Xilinx Virtex-4=20
>>FX series FPGA=92s, PPC405 processor?
>>
>> =20
>>
>
>Yes, see=20
>http://ozlabs.org/pipermail/linuxppc-embedded/2006-April/022583.html
>
>Note that there are silicon bugs that prevent caches being used in some=20
>chips.
>
> =20
>
>>More specifically, the FX100 FPGA?
>> =20
>>
>
>I don't have one of those, sorry.
>
>- aidan
>
>_______________________________________________
>Linuxppc-embedded mailing list
>Linuxppc-embedded@ozlabs.org
>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
> =20
>
next prev parent reply other threads:[~2006-06-01 17:06 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-05-31 19:02 Linux 2.4 Kernel on Xilinx Virtex4 FX100's PPC Anantharaman Chetan-W16155
2006-05-31 19:35 ` Grant Likely
2006-05-31 21:47 ` Anantharaman Chetan-W16155
2006-05-31 22:33 ` Grant Likely
2006-06-01 16:59 ` Peter Ryser
2006-05-31 23:14 ` Anantharaman Chetan-W16155
2006-05-31 22:22 ` Aidan Williams
2006-06-01 17:05 ` Peter Ryser [this message]
2006-06-01 17:08 ` Grant Likely
2006-06-01 18:03 ` Peter Ryser
2006-06-12 16:57 ` Stephen Telfer
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