From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from outbound1-cpk-R.bigfish.com (outbound-cpk.frontbridge.com [207.46.163.16]) (using TLSv1 with cipher EDH-RSA-DES-CBC3-SHA (168/168 bits)) (Client CN "*.bigfish.com", Issuer "*.bigfish.com" (not verified)) by ozlabs.org (Postfix) with ESMTP id 3445267A58 for ; Fri, 2 Jun 2006 03:06:02 +1000 (EST) Message-ID: <447F1E48.10808@xilinx.com> Date: Thu, 01 Jun 2006 10:05:12 -0700 From: Peter Ryser MIME-Version: 1.0 To: Aidan Williams Subject: Re: Linux 2.4 Kernel on Xilinx Virtex4 FX100's PPC References: <447E1725.4010908@nicta.com.au> In-Reply-To: <447E1725.4010908@nicta.com.au> Content-Type: text/plain; charset=windows-1252; format=flowed Cc: Anantharaman Chetan-W16155 , linuxppc-embedded@ozlabs.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , There are some silicon issues on the PPC405 in V4 with PVR 0x20011430=20 which are documented in Xilinx solution record 20658. All these issues=20 are fixed in silicon where the PPC405 has a PVR of 0x20011470. Said that it's not true that the caches cannot be used in silicon with=20 PVR 0x20011430. The problem is a corner case which does not show in=20 typical designs. - Peter Aidan Williams wrote: >Anantharaman Chetan-W16155 wrote: > =20 > >>Has anyone successfully ported a Linux 2.4 Kernel on a Xilinx Virtex-4=20 >>FX series FPGA=92s, PPC405 processor? >> >> =20 >> > >Yes, see=20 >http://ozlabs.org/pipermail/linuxppc-embedded/2006-April/022583.html > >Note that there are silicon bugs that prevent caches being used in some=20 >chips. > > =20 > >>More specifically, the FX100 FPGA? >> =20 >> > >I don't have one of those, sorry. > >- aidan > >_______________________________________________ >Linuxppc-embedded mailing list >Linuxppc-embedded@ozlabs.org >https://ozlabs.org/mailman/listinfo/linuxppc-embedded > > > =20 >