[PATCH 5/10 v2] Add 8641 CPU and i8259 Setup

[PATCH 5/10 v2] Add 8641 CPU and i8259 Setup

[Jon Loeliger]

Add 8641 CPU table entry.
Add SMP CPU id determination and clear BATS.
Use level triggers on i8259.

Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com>
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>

---

 arch/powerpc/kernel/cputable.c |   12 ++++++++++++
 arch/powerpc/kernel/head_32.S  |   15 +++++++++++++++
 arch/powerpc/sysdev/i8259.c    |    5 +++++
 3 files changed, 32 insertions(+), 0 deletions(-)


diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 0c487ee..2c8ac7e 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -704,6 +704,18 @@ #if CLASSIC_PPC
 		.oprofile_type		= PPC_OPROFILE_G4,
 		.platform		= "ppc7450",
 	},
+        {       /* 8641 */
+               .pvr_mask               = 0xffffffff,
+               .pvr_value              = 0x80040010,
+               .cpu_name               = "8641",
+               .cpu_features           = CPU_FTRS_7447A,
+               .cpu_user_features      = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
+               .icache_bsize           = 32,
+               .dcache_bsize           = 32,
+               .num_pmcs               = 6,
+               .cpu_setup              = __setup_cpu_745x
+        },
+
 	{	/* 82xx (8240, 8245, 8260 are all 603e cores) */
 		.pvr_mask		= 0x7fff0000,
 		.pvr_value		= 0x00810000,
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index a0579e8..e8f6bfa 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -224,6 +224,10 @@ turn_on_mmu:
 	li	r3,1			/* MTX only has 1 cpu */
 	.globl	__secondary_hold
 __secondary_hold:
+#ifdef CONFIG_PPC_86xx
+	/* get the cpu id */
+	mfspr	r3, SPRN_PIR
+#endif
 	/* tell the master we're here */
 	stw	r3,__secondary_hold_acknowledge@l(0)
 #ifdef CONFIG_SMP
@@ -348,6 +352,16 @@ #define EXC_XFER_EE_LITE(n, hdlr)	\
 #if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
 	. = 0x100
 	b	__secondary_start_gemini
+#endif
+/* we need to ensure that the address translation is disabled */
+#if defined(CONFIG_PPC_86xx) && defined(CONFIG_SMP)
+        . = 0x100
+        mfmsr   r3
+        andi.   r0, r3, (MSR_IR | MSR_DR)
+        andc    r3, r3, r0
+        mtmsr   r3
+        isync
+        b       __secondary_hold
 #else
 	EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
 #endif
@@ -1019,6 +1033,7 @@ #endif /* CONFIG_6xx */
 	stw	r0,0(r3)
 
 	/* load up the MMU */
+	bl	clear_bats
 	bl	load_up_mmu
 
 	/* ptr to phys current thread */
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
index b7ac32f..9b755e1 100644
--- a/arch/powerpc/sysdev/i8259.c
+++ b/arch/powerpc/sysdev/i8259.c
@@ -201,6 +201,11 @@ void __init i8259_init(unsigned long int
 	outb(0x0B, 0x20);
 	outb(0x0B, 0xA0);
 
+#ifdef CONFIG_I8259_LEVEL_TRIGGER
+	outb(0xfa, 0x4d0); /* level triggered */
+	outb(0xde, 0x4d1);
+#endif
+
 	/* Mask all interrupts */
 	outb(cached_A1, 0xA1);
 	outb(cached_21, 0x21);

Re: [PATCH 5/10 v2] Add 8641 CPU and i8259 Setup

[Benjamin Herrenschmidt]

> --- a/arch/powerpc/kernel/head_32.S
> +++ b/arch/powerpc/kernel/head_32.S
> @@ -224,6 +224,10 @@ turn_on_mmu:
>  	li	r3,1			/* MTX only has 1 cpu */
>  	.globl	__secondary_hold
>  __secondary_hold:
> +#ifdef CONFIG_PPC_86xx
> +	/* get the cpu id */
> +	mfspr	r3, SPRN_PIR
> +#endif

The above is wrong, it prevents using the same kernel image on another
platform. If you need a separate hold loop, then go for it but don't
change the existing one in a non-compatible way. Alternatively, you can
do like powermac, that is have several "entrypoints" to the same hold
loop providing different CPU IDs.

>  	/* tell the master we're here */
>  	stw	r3,__secondary_hold_acknowledge@l(0)
>  #ifdef CONFIG_SMP
> @@ -348,6 +352,16 @@ #define EXC_XFER_EE_LITE(n, hdlr)	\
>  #if defined(CONFIG_GEMINI) && defined(CONFIG_SMP)
>  	. = 0x100
>  	b	__secondary_start_gemini
> +#endif
> +/* we need to ensure that the address translation is disabled */
> +#if defined(CONFIG_PPC_86xx) && defined(CONFIG_SMP)
> +        . = 0x100
> +        mfmsr   r3
> +        andi.   r0, r3, (MSR_IR | MSR_DR)
> +        andc    r3, r3, r0
> +        mtmsr   r3
> +        isync
> +        b       __secondary_hold
>  #else
>  	EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
>  #endif

Same comment above... #ifdef is bad. You are entering from 0x100 with
address translation not disabled ? How is that possible ? If it's your
firmware, then fix it :) If not possible, then have a real good
explanation why and how you end up in 0x100 that way. At worse, do like
pmac does and "patch" the 0x100 vector to point to some machine specific
code dynamically at runtime. 

> @@ -1019,6 +1033,7 @@ #endif /* CONFIG_6xx */
>  	stw	r0,0(r3)
>  
>  	/* load up the MMU */
> +	bl	clear_bats
>  	bl	load_up_mmu

Why do you need to call clear_bats here ? load_up_mmu should load BATs.
If it doesn't handle the high BATs, then fix it :) 

>  	/* ptr to phys current thread */
> diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
> index b7ac32f..9b755e1 100644
> --- a/arch/powerpc/sysdev/i8259.c
> +++ b/arch/powerpc/sysdev/i8259.c
> @@ -201,6 +201,11 @@ void __init i8259_init(unsigned long int
>  	outb(0x0B, 0x20);
>  	outb(0x0B, 0xA0);
>  
> +#ifdef CONFIG_I8259_LEVEL_TRIGGER
> +	outb(0xfa, 0x4d0); /* level triggered */
> +	outb(0xde, 0x4d1);
> +#endif

Another change that breaks multiplatform... Can you explain precisely
what you are trying to acheive here ? If necessary, we can add an
argument to i8259_init. Or you could do the above in your platform
code ... though I agree it would be a bit ugly :) 

>  	/* Mask all interrupts */
>  	outb(cached_A1, 0xA1);
>  	outb(cached_21, 0x21);

Re: [PATCH 5/10 v2] Add 8641 CPU and i8259 Setup

[Jon Loeliger]

So, like, the other day Benjamin Herrenschmidt mumbled:
> 
> [A bunch of SMP issues.]
> 
> The above is wrong, it prevents using the same kernel image on another
> platform.

> Same comment above... #ifdef is bad. You are entering from 0x100 with
> address translation not disabled ?

> > +	bl	clear_bats
> >  	bl	load_up_mmu
> 
> Why do you need to call clear_bats here ? load_up_mmu should load BATs.
> If it doesn't handle the high BATs, then fix it :) 

> > +#ifdef CONFIG_I8259_LEVEL_TRIGGER
> > +	outb(0xfa, 0x4d0); /* level triggered */
> > +	outb(0xde, 0x4d1);
> > +#endif
> 
> Another change that breaks multiplatform... Can you explain precisely
> what you are trying to acheive here ? If necessary, we can add an
> argument to i8259_init. Or you could do the above in your platform
> code ... though I agree it would be a bit ugly :) 

OK.  I don't have direct answers in hand for some of
these questions and issues.  I'll get with original
authors and see what we can do clean this up!

Thanks!

jdl

Re: [PATCH 5/10 v2] Add 8641 CPU and i8259 Setup

[Xianghua Xiao]

Jon Loeliger wrote:

>So, like, the other day Benjamin Herrenschmidt mumbled:
>  
>
>>[A bunch of SMP issues.]
>>
>>The above is wrong, it prevents using the same kernel image on another
>>platform.
>>    
>>
>
>  
>
>>Same comment above... #ifdef is bad. You are entering from 0x100 with
>>address translation not disabled ?
>>    
>>
>
>  
>
>>>+	bl	clear_bats
>>> 	bl	load_up_mmu
>>>      
>>>
>>Why do you need to call clear_bats here ? load_up_mmu should load BATs.
>>If it doesn't handle the high BATs, then fix it :) 
>>    
>>
>
>  
>
I will fix this...

>>>+#ifdef CONFIG_I8259_LEVEL_TRIGGER
>>>+	outb(0xfa, 0x4d0); /* level triggered */
>>>+	outb(0xde, 0x4d1);
>>>+#endif
>>>      
>>>
>>Another change that breaks multiplatform... Can you explain precisely
>>what you are trying to acheive here ? If necessary, we can add an
>>argument to i8259_init. Or you could do the above in your platform
>>code ... though I agree it would be a bit ugly :) 
>>    
>>
>
>  
>
The above code is a must-have on our 8641D HPCN board to get PCI-Express 
ULI1575 southbridge going. The 8259(which is residing inside the 
southbridge) is collecting all PCI devices' interrupts( from both inside 
the ULI1575 and at its external PCI slots) before it reports to MPIC. 
PCI interrupts are level-triggered and shared thus we have to configure 
8259 to be level-triggered on this particular board.

>OK.  I don't have direct answers in hand for some of
>these questions and issues.  I'll get with original
>authors and see what we can do clean this up!
>
>Thanks!
>
>jdl
>_______________________________________________
>Linuxppc-dev mailing list
>Linuxppc-dev@ozlabs.org
>https://ozlabs.org/mailman/listinfo/linuxppc-dev
>  
>

Re: [PATCH 5/10 v2] Add 8641 CPU and i8259 Setup

[Jon Loeliger]

On Fri, 2006-06-09 at 11:05, Jon Loeliger wrote:

> > > +	bl	clear_bats
> > >  	bl	load_up_mmu
> > 
> > Why do you need to call clear_bats here ? load_up_mmu should load BATs.
> > If it doesn't handle the high BATs, then fix it :) 

Ben,

This line item has finally come around on the guitar!
And I have a question for you... 

How come this additional clear_bats call isn't seen
as a generic fix?  It is possible that the bootloader
has left some crufty (high) BATs hanging around.

Or are you suggesting just adding something like:

    li r10, 0
    mtspr SPRN_DBATxU,r10
    mtspr SPRN_DBATxL,r10

for x in (4 .. 7) to the tail end of load_up_mmu as
the general fix?

Thanks,
jdl