From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from nommos.sslcatacombnetworking.com (nommos.sslcatacombnetworking.com [67.18.224.114]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTP id D6600679FC for ; Mon, 28 Aug 2006 23:49:42 +1000 (EST) In-Reply-To: <995B09A8299C2C44B59866F6391D263511B945@zch01exm21.fsl.freescale.net> References: <995B09A8299C2C44B59866F6391D263511B945@zch01exm21.fsl.freescale.net> Mime-Version: 1.0 (Apple Message framework v752.2) Content-Type: text/plain; charset=US-ASCII; format=flowed Message-Id: <4495EF77-BC25-45B9-AC7B-BFCEBC619510@kernel.crashing.org> From: Kumar Gala Subject: Re: [QUESTION] Enable coherency for all pages on 83xx to fix PCI data corruption Date: Mon, 28 Aug 2006 08:49:41 -0500 To: Liu Dave-r63238 Cc: linuxppc-dev@ozlabs.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , This was to address PCI5 if I remember correctly. - kumar On Aug 28, 2006, at 2:49 AM, Liu Dave-r63238 wrote: > All, > > I want to know which PCI errata is solved by this patch > and if this patch did test on real hardware. > > I know this patch turn on the 'M' bit -memory coherency. > But I don't believe this can solved the "PCI read multi-line" > errata. > > -DAve > > http://ozlabs.org/pipermail/linuxppc-dev/2006-February/021267.html > > On the 83xx platform to ensure the PCI inbound memory is handled > properly we > have to turn on coherency for all pages in the MMU. Otherwise we see > corruption if inbound "prefetching/streaming" is enabled on the PCI > controller. > > Signed-off-by: Randy Vinson > Signed-off-by: Kumar Gala > > --- > > (For 2.6.16 if we can get it in) > > commit 4b2f4b1585f15d1c30cd2eda6d5f9a2ca7dcf998 > tree 7aebf508d10127831cf92fb7ce919230924ad85d > parent 7cfb7344aae902edfd5d51dd5f734cbf2585649c > author Kumar Gala Wed, 22 Feb 2006 > 09:53:34 -0600 > committer Kumar Gala Wed, 22 Feb 2006 > 09:53:34 -0600 > > include/asm-powerpc/cputable.h | 9 ++++++--- > 1 files changed, 6 insertions(+), 3 deletions(-) > > diff --git a/include/asm-powerpc/cputable.h > b/include/asm-powerpc/cputable.h > index 6421054..90d005b 100644 > --- a/include/asm-powerpc/cputable.h > +++ b/include/asm-powerpc/cputable.h > @@ -159,9 +159,11 @@ extern void do_cpu_ftr_fixups(unsigned l > #endif > > /* We need to mark all pages as being coherent if we're SMP or we > - * have a 74[45]x and an MPC107 host bridge. > + * have a 74[45]x and an MPC107 host bridge. Also 83xx requires > + * it for PCI "streaming/prefetch" to work properly. > */ > -#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) > +#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ > + || defined(CONFIG_PPC_83xx) > #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT > #else > #define CPU_FTR_COMMON 0 > @@ -277,7 +279,8 @@ enum { > CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE > | > CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | > CPU_FTR_HAS_HIGH_BATS, > CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE > | > - CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | > CPU_FTR_HAS_HIGH_BATS, > + CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | > CPU_FTR_HAS_HIGH_BATS | > + CPU_FTR_COMMON, > CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | > CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, > CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |