From: Michael Ellerman <patch-notifications@ellerman.id.au>
To: Nicholas Piggin <npiggin@gmail.com>, linuxppc-dev@lists.ozlabs.org
Cc: Nicholas Piggin <npiggin@gmail.com>
Subject: Re: [v4, 1/4] powerpc/64s: Fix HV NMI vs HV interrupt recoverability test
Date: Thu, 28 Feb 2019 20:21:11 +1100 (AEDT) [thread overview]
Message-ID: <4496Vb3v7Pz9s9T@ozlabs.org> (raw)
In-Reply-To: <20190226085110.29653-2-npiggin@gmail.com>
On Tue, 2019-02-26 at 08:51:07 UTC, Nicholas Piggin wrote:
> HV interrupts that use HSRR registers do not enter with MSR[RI] clear,
> but their entry code is not recoverable vs NMI, due to shared use of
> HSPRG1 as a scratch register to save r13.
>
> This means that a system reset or machine check that hits in HSRR
> interrupt entry can cause r13 to be silently corrupted.
>
> Fix this by marking NMIs non-recoverable if they land in HV interrupt
> ranges.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Series applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/ccd477028a202993b9ddca5d2404fdac
cheers
next prev parent reply other threads:[~2019-02-28 9:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-26 8:51 [PATCH v4 0/4] Fixes for 3 separate NMI reentrancy bugs Nicholas Piggin
2019-02-26 8:51 ` [PATCH v4 1/4] powerpc/64s: Fix HV NMI vs HV interrupt recoverability test Nicholas Piggin
2019-02-28 9:21 ` Michael Ellerman [this message]
2019-02-26 8:51 ` [PATCH v4 2/4] powerpc/64s: system reset interrupt preserve HSRRs Nicholas Piggin
2019-02-26 8:51 ` [PATCH v4 3/4] powerpc/64s: Prepare to handle data interrupts vs d-side MCE reentrancy Nicholas Piggin
2019-02-26 8:51 ` [PATCH v4 4/4] powerpc/64s: Fix " Nicholas Piggin
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