linuxppc-dev.lists.ozlabs.org archive mirror
 help / color / mirror / Atom feed
* Linux controlling Hardware-Tasks on FPGA
@ 2006-07-19  7:31 Josef Angermeier
  2006-07-19 16:15 ` David Hawkins
  0 siblings, 1 reply; 2+ messages in thread
From: Josef Angermeier @ 2006-07-19  7:31 UTC (permalink / raw)
  To: linuxppc-embedded


Hello,

anyone else out there using or wanting to use Linux to control the
reconfiguration of a FPGA ? - Do you use dynamic partial reconfiguration
too ? - If so how did you design the relevant software coarsely ?

thanks in advance,
Josef

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: Linux controlling Hardware-Tasks on FPGA
  2006-07-19  7:31 Linux controlling Hardware-Tasks on FPGA Josef Angermeier
@ 2006-07-19 16:15 ` David Hawkins
  0 siblings, 0 replies; 2+ messages in thread
From: David Hawkins @ 2006-07-19 16:15 UTC (permalink / raw)
  To: Josef Angermeier; +Cc: linuxppc-embedded


> anyone else out there using or wanting to use Linux to control the
> reconfiguration of a FPGA ? - Do you use dynamic partial reconfiguration
> too ? - If so how did you design the relevant software coarsely ?

Hi Josef,

If you are talking 'partial reconfiguration' then I guess you
are discussing Xilinx devices.

I use Altera devices in my designs. However, this solution could
work for you.

Generally an FPGA is configured, and I assume reconfigured,
by writing the configuration file to a specific set of pins
on the device. Altera devices have passive serial programming
and fast passive parallel programming (and other options).
In my current design I will create either a /dev entry or
use a /sys/firmware type interface that when opened
initializes the programming logic, and then writes whatever
bytes are written to the filesystem node to the programming
interface, eg. so the following will program the FPGA

dd if=firmware.bin of=/dev/fpga

If I get a programming error, then the driver can just return
-EIO, and I'm pretty sure dd will report the error. I plan
to use this approach as I can then buffer the data from user-space
into a kernel buffer, and then setup a DMA controller to
write to the device node. This will ensure that burst transactions
are used (to a system controller FPGA sitting on the local bus
of a PowerQUICC II Pro).

The alternative is to implement mmap() for the region containing
your programming interface control registers, and then just
bit- or byte-bang the programming interface. However, if the
serial interface is slow, then you could turn your 100MHz+ CPU
into a 1MHz- CPU. Linux sometimes has trouble with this
(I've seen the x86 kernel lose ticks when performing lots of
PCI I/O, so now use DMA when its available - which for x86
is basically never, so you have to depend on the adapter board).

Hope that gives you some ideas.

Regards
Dave

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2006-07-19 16:15 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2006-07-19  7:31 Linux controlling Hardware-Tasks on FPGA Josef Angermeier
2006-07-19 16:15 ` David Hawkins

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).