From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ug-out-1314.google.com (ug-out-1314.google.com [66.249.92.173]) by ozlabs.org (Postfix) with ESMTP id 2BA4067B5D for ; Fri, 25 Aug 2006 08:13:26 +1000 (EST) Received: by ug-out-1314.google.com with SMTP id e2so647938ugf for ; Thu, 24 Aug 2006 15:13:24 -0700 (PDT) Message-ID: <45a1b53e0608241513m5b97d34chf7e133eea984cb6c@mail.gmail.com> Date: Thu, 24 Aug 2006 17:13:24 -0500 From: "Wade Maxfield" To: "T Ziomek" Subject: Re: MontaVista 2.6 Kernel support for Xilinx ML40x In-Reply-To: MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_136940_8789329.1156457604309" References: <45a1b53e0608240836l52ed51b5u309e31dd8486cc5b@mail.gmail.com> <44EDD947.3000105@xilinx.com> <45a1b53e0608241057j4ebe519drd1e431a2275ccdde@mail.gmail.com> Cc: ppc List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , ------=_Part_136940_8789329.1156457604309 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline sorry! ;) See my reply at the right location! On 8/24/06, T Ziomek wrote: > > [top-posting fixed :-) ] > > > On Thu, 24 Aug 2006, Wade Maxfield wrote: > > > > On 8/24/06, Peter Ryser wrote: > >> > >> Wade, > >> > >> are you sure that you did not build your hardware with evaluation cores > of > >> the licenses? If you are using the evaluation licenses the hardware > (FPGA > >> design) will stop working after a certain amount of time and you will > see a > >> lock-up. > > > > Good question. How long before lockup? The only core that should be > > licensed is the ethernet, and I know it was sysgened on a system with a > > license. This is the Xilinx reference design for the ml403 board. > > When we were using the eval version of Xilinx's 10/100 EMAC it would time- > out after 8 hours (and the kernel would panic since our root fs was NFS- > mounted). > > If your only [to-be-]licensed core is Ethernet, then I take it you're > using > the UARTLite, or a non-Xilinx UART? We used Xilinx's 16550-compatible > UART, > which is licensed, but I never ran with the eval version of that IP block > and so have no idea how long it will function before shutting down. We are doing an evaluation right now. We have operational 8 hours 55 minutes so far and counting on the Xilinx 16550 compatible uart. I think that is the cause of the problem for us, but not sure so far. Tom > -- > A: Because it breaks the logical | > flow of the message. | Email to user 'CTZ001' > | at 'email.mot.com' > Q: Why is top posting frowned upon? | x<>y A2. but only for algebraic. RPN likes it that way. ------=_Part_136940_8789329.1156457604309 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline   sorry! ;)  See my reply at the right location!

On 8/24/06, T Ziomek <ctz001@email.mot.com> wrote:
[top-posting fixed  :-) ]


On Thu, 24 Aug 2006, Wade Maxfield wrote:
>
> On 8/24/06, Peter Ryser < peter.ryser@xilinx.com> wrote:
>>
>>  Wade,
>>
>> are you sure that you did not build your hardware with evaluation cores of
>> the licenses? If you are using the evaluation licenses the hardware (FPGA
>> design) will stop working after a certain amount of time and you will see a
>> lock-up.
>
> Good question.  How long before lockup?  The only core that should be
> licensed is the ethernet, and I know it was sysgened on a system with a
> license.  This is the Xilinx reference design for the ml403 board.

When we were using the eval version of Xilinx's 10/100 EMAC it would time-
out after 8 hours (and the kernel would panic since our root fs was NFS-
mounted).

If your only [to-be-]licensed core is Ethernet, then I take it you're using
the UARTLite, or a non-Xilinx UART?  We used Xilinx's 16550-compatible UART,
which is licensed, but I never ran with the eval version of that IP block
and so have no idea how long it will function before shutting down.


 We are doing an evaluation right now.  We have operational 8 hours 55 minutes so far and counting on the Xilinx 16550 compatible uart.  I think that is the cause of the problem for us, but not sure so far.
 

Tom
--
A: Because it breaks the logical        |
     flow of the message.                |   Email to user 'CTZ001'
                                         |             at 'email.mot.com'
Q: Why is top posting frowned upon?     |

x<>y
 A2. but only for algebraic.  RPN likes it that way.
 
 


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