Index: linux-2.6.20/arch/ppc/platforms/4xx/Kconfig =================================================================== --- linux-2.6.20.orig/arch/ppc/platforms/4xx/Kconfig +++ linux-2.6.20/arch/ppc/platforms/4xx/Kconfig @@ -55,12 +55,14 @@ config WALNUT config XILINX_ML300 bool "Xilinx-ML300" select XILINX_VIRTEX_II_PRO + select XSYSACE_8BIT help This option enables support for the Xilinx ML300 evaluation board. config XILINX_ML403 bool "Xilinx-ML403" select XILINX_VIRTEX_4_FX + select XSYSACE_16BIT_LE help This option enables support for the Xilinx ML403 evaluation board. endchoice Index: linux-2.6.20/drivers/block/Kconfig =================================================================== --- linux-2.6.20.orig/drivers/block/Kconfig +++ linux-2.6.20/drivers/block/Kconfig @@ -459,6 +459,16 @@ config XILINX_SYSACE help Include support for the Xilinx SystemACE CompactFlash interface +config XSYSACE_8BIT + bool + depends on XILINX_SYSACE + default n + +config XSYSACE_16BIT_LE + bool + depends on XILINX_SYSACE + default n + endmenu endif Index: linux-2.6.20/drivers/block/xsysace.c =================================================================== --- linux-2.6.20.orig/drivers/block/xsysace.c +++ linux-2.6.20/drivers/block/xsysace.c @@ -163,7 +163,39 @@ MODULE_LICENSE("GPL"); */ /* register access macros */ -#if 1 /* Little endian 16-bit regs */ + +#if defined CONFIG_XSYSACE_8BIT +/* Little endian 8-bit regs */ +#define ace_reg_read8(ace, reg) \ + in_8(ace->baseaddr + reg) +#define ace_reg_read16(ace, reg) \ + (in_8(ace->baseaddr + reg) | (in_8(ace->baseaddr + reg+1) << 8)) +#define ace_reg_readdata(ace, reg) \ + ((in_8(ace->baseaddr + reg) << 8) | (in_8(ace->baseaddr + reg+1))) +#define ace_reg_read32(ace, reg) \ + ( in_8(ace->baseaddr + reg) | \ + (in_8(ace->baseaddr + reg+1) << 8) | \ + (in_8(ace->baseaddr + reg+2) << 16) | \ + (in_8(ace->baseaddr + reg+3) << 24)) +#define ace_reg_write16(ace, reg, val) \ + do { \ + out_8(ace->baseaddr + reg, val); \ + out_8(ace->baseaddr + reg+1, (val) >> 8); \ + } while (0) +#define ace_reg_writedata(ace, reg, val) \ + do { \ + out_8(ace->baseaddr + reg, (val)>>8); \ + out_8(ace->baseaddr + reg+1, val); \ + } while (0) +#define ace_reg_write32(ace, reg, val) \ + do { \ + out_8(ace->baseaddr + reg, val); \ + out_8(ace->baseaddr + reg+1, (val) >> 8); \ + out_8(ace->baseaddr + reg+2, (val) >> 16); \ + out_8(ace->baseaddr + reg+3, (val) >> 24); \ + } while (0) +#elif defined CONFIG_XSYSACE_16BIT_LE +/* Little endian 16-bit regs */ #define ace_reg_read8(ace, reg) in_8(ace->baseaddr + reg) #define ace_reg_read16(ace, reg) in_le16(ace->baseaddr + reg) #define ace_reg_readdata(ace, reg) in_be16(ace->baseaddr + reg) @@ -171,11 +203,12 @@ MODULE_LICENSE("GPL"); (in_le16(ace->baseaddr + reg))) #define ace_reg_write16(ace, reg, val) out_le16(ace->baseaddr + reg, val) #define ace_reg_writedata(ace, reg, val) out_be16(ace->baseaddr + reg, val) -#define ace_reg_write32(ace, reg, val) { \ +#define ace_reg_write32(ace, reg, val) do { \ out_le16(ace->baseaddr + reg+2, (val) >> 16); \ out_le16(ace->baseaddr + reg, val); \ - } -#else /* Big endian 16-bit regs */ + } while (0) +#else +/* Big endian 16-bit regs */ #define ace_reg_read8(ace, reg) in_8(ace->baseaddr + reg) #define ace_reg_read16(ace, reg) in_be16(ace->baseaddr + reg) #define ace_reg_readdata(ace, reg) in_le16(ace->baseaddr + reg) @@ -183,10 +216,10 @@ MODULE_LICENSE("GPL"); (in_be16(ace->baseaddr + reg))) #define ace_reg_write16(ace, reg, val) out_be16(ace->baseaddr + reg, val) #define ace_reg_writedata(ace, reg, val) out_le16(ace->baseaddr + reg, val) -#define ace_reg_write32(ace, reg, val) { \ +#define ace_reg_write32(ace, reg, val) do { \ out_be16(ace->baseaddr + reg+2, (val) >> 16); \ out_be16(ace->baseaddr + reg, val); \ - } + } while (0) #endif struct ace_device {